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november 1996 1 copyright ? 1996 by lsi logic corporation. all rights reserved. minirisc? MR4010 superscalar microprocessor reference device contents 1 MR4010 features 7 2 MR4010 functional blocks 9 2.1 cw4010 shell 10 2.2 synchronous dram controller (dramc) 12 2.3 scbus to local i/o bus (lbus) controller (sclc) 12 2.4 pll clock circuit 12 3 MR4010 programming model 13 4 signal descriptions 13 4.1 scbus interface 14 4.2 external buffering for scbus signals 21 4.3 cw4010 shell interface 24 4.4 mbus interface 26 4.5 lbus interface 28 4.6 phase-locked loop (pll) clock signals 31 4.6 test signals 32 4.7 cw4010 core monitor signals 33 5 pll circuit 36 6 system con?guration 37 6.1 cw4010 ccc register 37 6.2 lbus controller registers 41 7 MR4010 memory map 42 8 cw4010 instruction set summary 43 9 dram controller and memory bus 55 9.1 dram types and available dram address area 55 9.2 memory interface 56 9.3 address bit assignment 58 9.4 dram modes and programmable con?gurations 59 9.5 dram refresh 67 9.6 dram commands 69 9.7 initializing the dram and programming the mode
2 minirisc MR4010 superscalar microprocessor register 71 9.8 dram transactions 76 10 local i/o bus and scbus/lbus converter module 80 10.1 lbus features 80 10.2 MR4010 as master on the lbus 81 10.3 MR4010 as slave on the lbus 83 10.4 scbus timeout watchdog timer 85 10.5 external vectored interrupt (evint) support 86 11 cache con?guration and maintenance 87 11.1 cache con?guration 87 11.2 cache maintenance 89 12 organization of speci?c internal signals 89 12.1 clock circuitry 89 12.2 exception inputs 91 13 electrical characteristics 93 14 package information 96
minirisc MR4010 superscalar microprocessor 3 figures 1 block diagram of MR4010 and evaluation board circuitry 7 2 MR4010 reference device block diagram 9 3 block diagram of cw4010 shell modules and cw4010 core 10 4 MR4010 buses 14 5 scbus interface 15 6 buffering for scap[31:0] address bus 21 7 buffering for scdp[63:0] data bus 22 8 buffering for scben[7:0] byte enable 23 9 shell interface overview 24 10 mbus and lbus interface 27 11 MR4010 pll circuit diagram 36 12 cw4010 ccc register 37 13 MR4010 master/slave memory map 43 14 MR4010 interface with dram 57 15 scbus dram address bit assignment 58 16 dram mode register format 60 17 dram controller con?guration register format 62 18 dram refresh interval timer 68 19 timing requirements for the dram initialization sequence 75 20 single burst read transaction 77 21 two continuous single write transactions 78 22 burst write transaction 79 23 timing requirements for an scbus-to-lbus transaction 82 24 timing requirements for lbus-to-scbus transaction 84 25 scbus error address and status register bit format 85 26 external vectored interrupt register bit format 86 27 MR4010 pll clock circuitry 90 28 timing requirements for the cw4010 and lbus clocks 91 29 exception inputs synchronization circuitry 92 30 timing requirements for synchronization circuit 92 31 ac timing for MR4010 inputs and outputs 96 32 mechanical drawing of the 299-pin cpga (ft) MR4010 device 97
4 minirisc MR4010 superscalar microprocessor tables 1 bus error internal registers 42 2 MR4010 (cw4010) instruction set summary 44 3 dram con?gurations 56 4 scbus address and mbus address bit assignment 59 5 relationship between frequency and latency 67 6 refresh register programming values 69 7 summary of dram commands and mbus control signals 70 8 timing signals 73 9 timing diagram abbreviations 74 10 cache size and accessing 88 11 dcache scratchpad ram con?guration 88 12 icache scratchpad ram con?guration 89 13 summary of MR4010 clocks 91 14 absolute maximum ratings 93 15 recommended operating conditions 93 16 input/output capacitance 93 17 dc characteristics 94 18 MR4010 ac timing speci?cations 95 19 MR4010 pin assignments 99
minirisc MR4010 superscalar microprocessor 5
6 minirisc MR4010 superscalar microprocessor overview the minirisc MR4010 microprocessor reference device is a chip implementation of the minirisc cw4010 microprocessor core and shell. the MR4010 contains the following circuitry: the cw4010 shell, which is an unencrypted verilog model contain- ing the cw4010 core, the multiply/divide unit, instruction cache (icache), data cache (dcache), memory management unit (mmu), and a writeback buffer a dram controller (dramc) that controls the memory bus and an external synchronous dram array an scbus/lbus converter (sclc) that controls the local i/o bus and external lbus devices a phase-locked loop (pll) circuit that supplies clock inputs to the other modules in the MR4010 the MR4010 uses the maximum con?guration cw4010 shell. you can disable optional modules by programming the con?guration register in the cw4010 cores coprocessor 0 (cp0). MR4010 functional blocks, starting on page 9 , provides further information about the different elements of the MR4010. the MR4010 is housed on an evaluation board that allows you to use and test the microprocessor. in addition to the MR4010 reference device, the board also contains the dram array and lbus facilities for plugging in devices such as a boot-rom, serial i/o devices, and an external ethernet controller. figure 1 provides a block diagram of the MR4010 evaluation board circuitry.
minirisc MR4010 superscalar microprocessor 7 figure 1 block diagram of MR4010 and evaluation board circuitry 1 MR4010 features the MR4010 reference device has the following features: superscalar microprocessor supports the mips-ii 32-bit instruction set: C executes up to two instructions per clock cycle C four-deep write buffer C load scheduling C r3000/r4000 compatible mode for exception return and status register 32-bit timer (r4000 compatible) scbus watchdog timer with error reporting features full internal scan testing local iobus (lbus) interface C subset of the vlbus (486 bus); does not have i/o space, data/code, inta, support for burst transactions C demultiplexed 32-bit address bus and 32-bit data bus synchronous local iobus (lbus) main memory MR4010 reference device scbus cache invalidation scbus/lbus converter scbus boot-rom serial i/o mbus (sclc) synchronous controller ethernet controller (sonic) (dramc) cw4010 dram dram phase-locked loop (pll) cell shell md96.262 evaluation board
8 minirisc MR4010 superscalar microprocessor direct interface to the sonic? ethernet controller synchronous dram controller, with 64-bit wide data transfer, interfaces to the following 16-mbit drams: C 1-mword x 16-bit dram devices in an 8-mbyte or 16-mbyte con?guration C 2-mword x 8-bit dram devices in a 16-mbyte or 32-mbyte con?guration C 4-mword x 4-bit dram devices in an 32-mbyte or 64-mbyte con?guration pll circuit for system clock 3.3 v operation up to 66 mhz microprocessor clock packaged in a 299-pin cpga (ceramic pin-grid array package) maximum cw4010 con?guration: C direct-mapped or two-way set-associative icache and dcache C 1-kbyte, 2-kbyte, 4-kbyte, or 8-kbyte cache sets; organized as either direct-mapped (single set) cache with maximum cache size of 8 kbytes, or as two-way set-associative cache with a maximum cache size of 16 kbytes. C memory management unit with 32-entry fully associative tlb (translation lookaside buffer) C fast multiplier supporting multiply-accumulate operations
minirisc MR4010 superscalar microprocessor 9 2 MR4010 functional blocks this section describes the functional blocks that make up the MR4010 reference device: cw4010 shell scbus/lbus converter dram controller pll clock circuit figure 2 shows the relationship between these blocks. figure 2 MR4010 reference device block diagram local io bus memory bus (lbus) (mbus) MR4010 reference device scbus cache invalidation synchronous controller (dramc) dram pll clock circuit scbus/lbus converter (sclc) cw4010 shell md96.263
10 minirisc MR4010 superscalar microprocessor 2.1 cw4010 shell the cw4010 shell consists of the cw4010 core and a number of optional modules, including icache, dcache, the multiply/divide unit, the mmu (memory management unit), and the writeback buffer. you can modify the modules in the shell to ?t your own asic design. figure 3 shows a block diagram of the shell modules. figure 3 block diagram of cw4010 shell modules and cw4010 core 2.1.1 cw4010 core the cw4010 core is part of lsi logics coreware ? library. it is an encrypted synthesizable verilog model. as shown in figure 3 , it contains the basic microprocessor elements: arithmetic logic unit (alu) instruction scheduling unit (isu) load/store unit (lsu) bus interface unit (biu) coprocessor 0 (cp0) the core is a hardmacro. it remains the same for each asic design, and can easily be reused. reset, interrupts scbus coprocessor interface cache invalidation cw4010 core interface oca interface interface multiply/ divide alu mmu writeback buffer dcache set-0 dcache set-1 cp0 isu lsu biu unit icache set-0 icache set-1 cw4010 shell
minirisc MR4010 superscalar microprocessor 11 the cw4010 core executes all mips-ii 32-bit based instructions except for multiply/divide instructions, which are handled by the multiply/divide unit. the microprocessor is implemented as ef?cient dual six-stage pipelines. the pipelines have the traditional instruction fetch and execu- tion stages. an additional queuing (q) stage (one of the instruction fetch stages) removes the penalty cycle when a branch instruction is executed. standard mips compiled code for r3000 and r4000 processors runs on the cw4010 core. the cw4010 has an extended instruction set and implements addciu (add with circular mask immediate unsigned), madd/maddu (multiply accumulate (unsigned)), msub/msubu (multiply subtract (unsigned)), ffs/ffc (find first set/clear bit), selsr/selsl (select and shift right/left), waiti (wait interrupt) and flushid (flush instruction/data cache) instructions. 2.1.2 multiply/divide the multiply/divide module supports multiply-add/subtract operations as well as multiply and divide. the multiply instruction executes in three cycles. the multiply-add/subtract instruction is optimized to two cycles. 2.1.3 memory management unit (mmu) the mmu has 32 single-page entries, which are a subset of the r4000 32-bit addressing mode. each page is individually speci?ed to be 4 kbyte or 16 mbyte and may be cached or uncached. 2.1.4 writeback buffer the cw4010 uses this buffer when the dcache operates in writeback mode. when a cache miss occurs at a dirty line, the dirty data is written into the writeback buffer instead of the main memory. this reduces the latency of the cache re?ll for missed addresses. data in the writeback buffer is written into the main memory after the re?ll is completed. 2.1.5 caches the MR4010 has separate instruction and data cachesicache and dcachethat are part of the cw4010 shell. both caches can be orga- nized as direct-mapped or two-way set-associative caches. the cache controllers support con?gurations of 1, 2, 4, or 8 kbytes for each set.
12 minirisc MR4010 superscalar microprocessor thus, the smallest supported con?guration is a 1 kbyte direct-mapped cache, and the largest is a 16 kbyte two-way set-associative cache, with 8 kbytes per set. you can select between writeback and writethrough modes. you can also con?gure the dcache for scratch pad ram mode. 2.2 synchronous dram controller (dramc) the dram controller is part of the MR4010 reference device external to the cw4010 shell. it generates dram transactions according to requests from the cw4010 core or from the sclc module. the dram controller also generates initialization cycles and refresh cycles for dram. 2.3 scbus to local i/o bus (lbus) controller (sclc) the sclc module is part of the MR4010 reference device external to the cw4010 shell. it provides an interface between the internal cw4010 microprocessor bus, (scbus), and the external local i/o bus (lbus). the lbus connects boot-rom, serial i/o devices, and the ethernet controller to the MR4010. the cw4010 scbus is a 32-bit address, 64-bit data bus. the lbus, which is a subset of the industrial standard vlbus, is a 32-bit address, 32-bit data bus. the cw4010 uses the sclc module to access devices on the lbus. devices on the lbus access the dram main memory through the sclc module and the dram controller. the cw4010 microprocessor generally has ownership of the scbus and the lbus. when a device on the lbus wants to access the dram, it asserts the bus hold request signal on the lbus. the sclc module detects the asserted signal and then asserts the bus hold request to the cw4010. the cw4010 asserts the grant signal to the sclc module, and the sclc module then asserts the hold acknowledge signal to the lbus device. 2.4 pll clock circuit the pll circuit is part of the MR4010 reference device external to the cw4010 shell. it drives the clock signals to the cw4010 shell and the other modules that are part of the MR4010.
minirisc MR4010 superscalar microprocessor 13 3 MR4010 programming model the term programming model refers to the way data is arranged in registers and in memory. you will ?nd information on these subjects in the following areas of this technical summary: system con?guration on page 37 dram modes and programmable con?gurations on page 59 scbus timeout watchdog timer on page 85 cache con?guration and maintenance on page 87 in addition, minirisc cw4010 superscalar microprocessor core technical manual provides information about the memory management unit and coprocessor 0 (cp0). 4 signal descriptions this section describes the MR4010 signals in the following groupings: scbus interface the interface between the cw4010 shell and the dramc and the sclc module implemented by means of the scbus. external buffering required for certain scbus signals. cw4010 shell interface other signals that interface between the cw4010 shell and the dramc and sclc. mbus interface the interface between the dram controller and the dram array, with inputs and outputs referenced to the MR4010 reference device. lbus interface the interface between the sclc and devices on the lbus, with inputs and outputs referenced to the MR4010 reference device. phase-locked loop (pll) interface the interface between the pll clock generator and the cw4010 shell, with inputs and outputs referenced to the cw4010 shell.
14 minirisc MR4010 superscalar microprocessor test signals input pins that allow lsi logic to test the MR4010. core monitor signals output signals that allow you to monitor the behavior of the cw4010 core. figure 4 shows the three major buses. each signal de?nition contains the mnemonic and the full signal name. active low signals have an n suf?x, for example, scresetn. active high signals have a p suf?x, for example, mdqmp. assert means to drive the signal true or active. deassert means to drive the signal false or inactive. figure 4 MR4010 buses 4.1 scbus interface figure 5 shows how the cw4010 shell uses the scbus to interface with the MR4010 reference devices sclc module and dram controller. in the interface between the cw4010 and the sclc, either module can function as the bus master or slave. in the interface between the cw4010 and the dram controller, the cw4010 is always the master. figure 5 also shows the cache invalidation signals input to the cw4010 shell from the sclc, and the address and write enable signal interface and the bus ready signal interface between the dramc and the sclc. MR4010 lbus devices dram controller cw4010 shell reference device lbus mbus scbus scbus interface, beginning on page 14. lbus interface, beginning on page 28. mbus interface, beginning on page 26. synchronous dram scbus/lbus converter md96.265
minirisc MR4010 superscalar microprocessor 15 you will need to provide external buffering for certain scbus signals. external buffering for scbus signals on page 21 provides information on this subject. figure 5 scbus interface sctpwn sclockn sctbstn scben[7:0] sctssn scdoen scdp[63:0] scaoen scap[31:0] schgtn sctsen scbrdyn scbpwan scbrtyn scberrn scb32n schrqn dram controller scbus/lbus controller cw4010 shell slaoen slwrn drrdyn dcinvsn icinvsn
16 minirisc MR4010 superscalar microprocessor schrqn bus hold request input to shell from sclc schrqn indicates that a device on the lbus is request- ing ownership of the scbus. bus hold request has the highest priority during bus arbitration. however, it cannot break continuous transactions of in-page writes and burst read/write transactions if those transactions are sup- ported by an asserted sctsen, and schrqn must wait until sctsen is deasserted. scb32n 32-bit bus width sizing input to shell from sclc scb32n indicates that the external bus slave on the sc bus needs 32-bit bus sizing. the cw4010 core samples this signal on the rising edge of the clock that synchro- nizes the scbus ready signal, scbrdyn. if scb32n is asserted for a 64-bit transaction, which is a doubleword or part of a burst transaction, the bus interface unit in the cw4010 core generates a subsequent 32-bit word trans- action and packs data to 64 bits for a read transaction or unpacks data to 32 bits for a write transaction. scberrn bus error input to shell from sclc the lbus master device asserts scberrn to terminate the current transaction when a bus error occurs. if scbrdyn, or the bus retry signal, scbrtyn, is asserted at the same time as scberrn, scberrn has higher priority. scberrn is reported to the cp0 and the cp0 generates an exception. scbrtyn bus retry input to shell from sclc the lbus master device asserts scbrtyn when the current transaction has been terminated unsuccessfully and must be retried later. the control state goes back once to the idle state, then all bus requests are arbitrated again. if there are no higher priority requests and the lbus master has asserted sctsen, there is one idle state between the ?rst transaction and a retry transaction. if scbrdyn and scbrtyn are asserted at the same time, scbrtyn has the higher priority. scap[31:0] address bus bidirectional between shell and sclc input to dramc scap[31:0] is the 32-bit address bus for instruction fetch and data read/write operations. the bus signals are valid only when the address output enable signal, scaoen, is asserted. the enable signal remains valid throughout the
minirisc MR4010 superscalar microprocessor 17 operation until scbrdyn, scbrtyn, or scberrn is asserted. the cw4010 asserts the signals on this bus and outputs them to the sclc or the dramc. the lbus master can also assert scap[31:0] and output them to the cw4010 shell through the sclc. scaoen address output enable output from shell to dramc when the cw4010 asserts this signal, it indicates that the address bus lines, scap[31:0], are valid. the signal remains active throughout the bus transaction. scaoen also enables sctbstn, sctben, and sctpwn. this signal is not valid at the same time as slaoen, which is the address output enable signal output from the sclc shell to the dramc described on page 20 . scdp[63:0] data bus bidirectional between shell, sclc, and dramc scdp[63:0] are the data bus signals. they are output from the shell for data read/write operations and for data writeback to the dcache. they are input to the shell for data read and instruction fetch transactions. the cw4010 shell samples the signals on the rising edge of the clock when scbrdyn is asserted.the signals are valid throughout a write transaction where the cw4010 is writing to dram through the dramc, or the lbus device is writing to the cw4010 or dramc through the sclc. byte ordering is little endian. scdoen data output enable output from shell to sclc and dramc the cw4010 asserts scdoen throughout a write trans- action and outputs it to the sclc or the dramc. the signal indicates that the current transaction is a write transaction, and it also enables data output. it performs the same function for a cw4010 write transaction to dram that slwrn ( page 20 ) performs for an sclc write transaction to dram. sctssn transaction start strobe output from shell to sclc the cw4010 asserts sctssn for one clock cycle at the beginning of a transaction to indicate that a transaction has started. if the next transaction begins immediately, the cw4010 asserts sctssn continuously.
18 minirisc MR4010 superscalar microprocessor scben[7:0] byte enable bidirectional between shell and sclc and input to dramc scben[7:0] indicate which byte positions are valid for a read or write transaction. the cw4010 asserts the signals and outputs them to the sclc or the dramc. the lbus device can also assert the signals and input them to the cw4010 through the sclc. only one of the signals is asserted during a byte read or byte write trans- action. all signals are asserted for a doubleword or burst transaction. sctbstn burst transaction output from shell to dramc the cw4010 asserts sctbstn and outputs it to the dramc to indicate that a transaction is taking place during which four doublewords will be moved, and that the ?rst doubleword is currently being moved. it deas- serts the signal after the ?rst word has been transferred and during singleword transactions. sclockn bus lock output from shell to sclc the cw4010 asserts sclockn to indicate that it wishes to lock the scbus and restrict ownership. the cw4010 asserts the signal when a read transaction is started by executing a loadlink instruction in an uncached area or a writethrough cached area. it deasserts the signal just before a write transaction is started by executing a store- conditional instruction. during read and write transac- tions, the cw4010 asserts the signal continuously, preventing ownership from changing during one of these transactions. if a storeconditional transaction hits the dcache in a writeback cached read while sclockn is asserted, an incorrect condition exists, and the cw4010 deasserts sclockn without completing any bus transactions. sctpwn next transaction is in-page write output from shell to dramc when asserted, this signal indicates that the next trans- action is in the same dram page as de?ned in the con?guration register. when the cw4010 asserts sctpwn, a maximum of four write transactions take place one after the other, even if there is an instruction fetch request or data read request. if there are four continuous write transactions, the cw4010 asserts sctpwn from the ?rst through the last (fourth)
minirisc MR4010 superscalar microprocessor 19 transaction. the cw4010 asserts sctpwn from the beginning of one in-page write transaction to the end of that transaction. the write buffer in the cw4010s lsu checks to see if the subsequent write request is in the same page. schgtn bus hold grant output from shell to sclc the cw4010s bus interface unit enters the hold state and asserts schgtn to indicate that it is releasing scbus ownership in response to a bus hold request (schrqn) from one of the devices on the lbus. sctsen transaction start enable input to shell from sclc sctsen enables or disables a new scbus transaction. transaction requests are arbitrated only when sctsen is asserted. the lbus device must deassert then assert the signal when scbrdyn is asserted to allow an idle cycle between the two transactions. during the time sctsen is deasserted, the cw4010s bus interface unit repeats the idle state. scbrdyn bus ready input to shell from sclc the sclc asserts scbrdyn when the current transac- tion is terminated, indicating that the scbus is available. the signal remains active (low) until the next transaction starts. the sclc deasserts the signal to indicate that the scbus is not available. the sclc receives a bus-ready signal, drrdyn from the dramc (see page 20 ), merges drrdyn with its own bus ready signal, and drives scbrdyn, which is output to the cw4010 shell. scbpwan bus in-page write accept input to shell from dramc the dramc asserts scbpwan to indicate that it accepts in-page write transactions. the cw4010 samples the signal on the rising edge of the clock that synchronizes scbrdyn. if the cw4010 has not asserted sctpwn, asserting or deasserting scbpwan has no signi?cance.
20 minirisc MR4010 superscalar microprocessor icinvsn icache invalidation strobe input to shell from sclc the sclc asserts this signal to indicate that the icache invalidation address bus is valid and there is no need for a snooping sequence. if the cache tag is not coincident with higher address bits, the line is not invalidated. dcinvsn dcache invalidation strobe input to shell from sclc the sclc asserts this signal to indicate that the dcache invalidation address bus is valid and there is no need for a snooping sequence. if the cache tag is not coincident with higher address bits, the line is not invalidated. slaoen address output enable output from sclc to dramc when the sclc asserts this signal, it indicates that the address bus lines, scap[31:0], are valid. the signal remains active throughout the bus transaction. scaoen also enables sctbstn, sctben, and sctpwn. this signal is not valid at the same time as scaoen, which is the address output enable signal output from the cw4010 shell to the sclc described on page 17 . slwrn sclc write enable output from sclc to dramc the sclc asserts this signal throughout a dram write operation and outputs it to the dramc. it performs the same function for a cw4010 write transaction to dram that slwrn ( page 17 ) performs for an sclc write trans- action to dram. drrdyn dram ready output from dramc to sclc the dramc asserts drrdyn when the current dram transaction is terminated, indicating that the bus is avail- able. the signal remains active (low) until the next transaction starts. the dramc outputs the signal to the sclc, which merges drrdyn with its own bus ready signal (see page 19 ), and drives scbrdyn, which is output to the cw4010 shell.
minirisc MR4010 superscalar microprocessor 21 4.2 external buffering for scbus signals you must provide external buffering for certain scbus signals, including address bus scap[31:0] address output enable signal scaoen and slaoen sc data bus scdp[63:0] data output enable scdoen scbus byte enable scben[7:0] figure 6 shows an example of a buffer con?guration in which the bidirec- tional address bus is buffered at the sclc and cw4010 ends by bts4a*32 3-state buffers. when the cw4010 asserts scaoen, the signal enables the buffer at the cw4010 end. when the sclc asserts slaoen, the signal enables the buffer at the sclc end. figure 6 buffering for scap[31:0] address bus dcinvap[31:5] icinvap[31:5] scaop[31:0] scaoen cw4010 shell draip[31:0] slaip[31:0] slaop[31:0] slaoen sclc dramc scap[31:0] buffer bts4a*32 buffer bts4a*32 bus holder bhd1a*32 md96.296
22 minirisc MR4010 superscalar microprocessor figure 7 shows an example of a buffer con?guration in which the sc data bus is buffered at the sclc and cw4010 ends by bts4a*64 3-state buffers. when the cw4010 asserts scdoen, the signal enables the buffer at the cw4010 end. when the sclc asserts sldoen, the signal enables the buffer at the sclc end. a bts4a*64 buffer also buffers the data output from the dramc. this buffer is enabled when the dramc asserts drdoen. figure 7 buffering for scdp[63:0] data bus dramc scdip[63:0] scdop[63:0] scdoen cw4010 shell drdip[63:0] sldip[63:0] sldop[63:0] sldoen sclc scdp[63:0] buffer bts4a*64 buffer bts4a*64 bus holder bhd1a*64 md96.297 drdop[63:0] drdoen buffer bts4a*64
minirisc MR4010 superscalar microprocessor 23 figure 8 shows an example of a buffer con?guration in which the sc byte enable signals, sctben[7:0], are buffered at the sclc and cw4010 ends by bts4a*8 3-state buffers. when the cw4010 asserts scaoen, the signal enables the buffer at the cw4010 end. when the sclc asserts slaoen, the signal enables the buffer at the sclc end. figure 8 buffering for scben[7:0] byte enable sctben[7:0] scaoen cw4010 shell drbein[7:0] slbein[7:0] slbeon[7:0] slaoen sclc buffer bts4a*8 buffer bts4a*8 bus holder bhd1a*8 md96.298 scben[7:0] dramc
24 minirisc MR4010 superscalar microprocessor 4.3 cw4010 shell interface figure 9 shows the internal interface that links the cw4010 shell, the sclc, and the dramc. "scbus interface" beginning on page 14 describes the scbus interface between these modules. figure 9 shell interface overview exvintn external vectored input input to shell from sclc the sclc drives this signal. when the cw4010 shell receives the signal, it generates an external interrupt exception. exvap[31:2] external vectored interrupt address input to shell the cw4010 shell accepts the external vectored interrupt address when the sclc asserts exvapen. the cw4010 writes the address directly into the program counter. the address bus must remain stable until exvapen is asserted. exvaen exvap enable output from shell to sclc this is the enable signal for the vectored interrupt address. the cw4010 asserts this signal to acknowledge the address. cw4010 shell sexint[5:0] snmin swresetn scresetn inputs strapped scbus/lbus converter dram controller frcmn bendn high md96.266 exvintn exvap[31:2] exvaen
minirisc MR4010 superscalar microprocessor 25 sexintn[5:0] external interrupt input [5:0] input to shell the dramc or sclc asserts one of the sexintn signals to cause the cp0 in the cw4010 core to gener- ate an interrupt exception. the assertion is registered in the ip ?eld of the cw4010 cause register. the sclc should continue to assert the signals until the exception routine has serviced the interrupt. the cw4010 does not recognize interrupts if the interrupt enable bit in the status register is not set. the cw4010 can therefore disable individual interrupt inputs by clearing the related bits. however, the interrupt inputs are still registered in the ip ?eld of the cause register. external interrupt input [5:0] are synchronized to the system clock, sclkp, internally in the cw4010 shell. snmin nonmaskable interrupt input to shell this input is synchronized internally to the system clock, sclkp. when the sclc asserts this signal, the cw4010 recognizes a nonmaskable interrupt. the cp0 then generates a nonmaskable interrupt exception (0xbfc0 0000). swresetn warm reset input to shell this input initiates a warm reset for the MR4010. inside the MR4010, this signal is synchronized to the system clock, sclkp. the MR4010 enters the warm reset condition when the sclc asserts swresetn and immediately exits from the warm reset when the sclc deasserts swresetn. screset cold reset input to shell this input initiates a cold reset for the MR4010. inside the MR4010, this signal is synchronized to the system clock, sclkp. the MR4010 enters the cold reset condition when the sclc asserts scresetn and immediately exits from the cold reset when the sclc deasserts scresetn. frcmn force cache miss (strap input) input to shell this input is used for system debug. under normal operating conditions, you should strap it high. to use it for debug, you should assert it by tying it low. when low, it forces a cache miss for the icache and the
26 minirisc MR4010 superscalar microprocessor dcache in the cw4010 shell. the cw4010 treats this event as an access to an uncached area. the cw4010 can then read and write all instructions and data as uncached, regardless of the memory segment and the mmu. bendn big endian (strap input) input to shell this input affects the byte positions for sizing and load/store data alignment. when the input is low (asserted), the cw4010 uses big-endian addressing. the MR4010 uses only little-endian addressing, so you tie this input high. 4.4 mbus interface figure 10 shows the 89 mbus signals that the MR4010 uses to connect the MR4010 dram controller to the synchronous drams in the main memory array. inputs and outputs are referenced to the dram controller. map[11:0] multiplexed memory address bus output these multiplexed signals carry row and column addresses. mrasn strobes the row addresses into the drams, and mcasn strobes the column addresses. address bit assignment on page 58 provides detailed information about the address bus. during memory initialization, the dram controller uses map[11:0] to write the 12-bit mode register in each dram. mdp[63:0] memory data bus bidirectional this 64-bit bidirectional data bus carries data between the MR4010 and the memory array. the direction of data ?ow is controlled by mwen. mcsn[1:0] memory chip select output mcsn[1:0] select between banks 0 and 1 in the dram array. the dram controller asserts mscn0 to select the drams that make up bank 0, and asserts mscn1 to select the drams in bank 1. if only one bank of drams is installed, the dram controller asserts mcsn0. mrasn memory row address strobe output the MR4010 asserts mrasn to strobe memory row addresses into the memory devices.
minirisc MR4010 superscalar microprocessor 27 mcasn memory column address strobe output the MR4010 asserts mcasn to strobe memory column addresses into the memory devices. mwen memory write enable output the MR4010 asserts mwen to enable a write operation and deasserts mwen to enable a read operation. figure 10 mbus and lbus interface lbus devices scbus synchronous mbus strap high strap low lcresetn lchalfn lclkp lap[31:2] ldp[31:0] lben[3:0] lrdn ladsn lrdyn lrtyn lholdp lhldap lbus map[11:0] mdp[63:0] mcsn[1:0] mrasn mcasn mwen mdqmp[7:0] MR4010 dram controller cw4010 shell reference device scbus/lbus converter dram array md96.267
28 minirisc MR4010 superscalar microprocessor mdqmp[7:0] memory data enable/mask output this is an 8-bit data mask used only during write opera- tions. when asserted, each bit of the mask selects one byte of data, as shown in the examples below, to enable write operations in individual bytes of the data word. during read operations, the dram controller asserts all the mask bits to select all data bytes. 4.5 lbus interface figure 10 shows the 75 lbus signals that connect the sclc in the MR4010 with external lbus devices. the MR4010 functions as the bus master to access external devices on the lbus, such as boot-rom, serial devices, and the ethernet controller. these lbus devices can also func- tion as bus master to access the dram through the sclc and the dramc. this section describes the signals on the lbus. inputs and outputs are referenced to the MR4010. since the MR4010 or an lbus device can be bus master, some signals that are typically unidirectional, such as the read signal lrdn, are bidirectional. when the MR4010 is bus master and asserts lrdn, it enables a read operation in one of the lbus devices. when an lbus device is bus master, it can assert lrdn to read data from the dram. mask byte selected dram byte/number 8-bit wide dram mdqmp 7 mdp[63:56] 7 mdqmp 6 mdp[55:48] 6 mdqmp 5 mdp[47:40] 5 mdqmp 4 mdp[39:32] 4 mdqmp 3 mdp[31:24] 3 mdqmp 2 mdp[23:16] 2 mdqmp 1 mdp[15:8] 1 mdqmp 0 mdp[7:0] 0 mask byte selected dram byte/number 16-bit wide dram mdqmp 7 mdp[63:56] 3 (upper byte) mdqmp 6 mdp[55:48] 3 (lower byte) mdqmp 5 mdp[47:40] 2 (upper byte) mdqmp 4 mdp[39:32] 2 (lower byte) mdqmp 3 mdp[31:24] 1 (upper byte) mdqmp 2 mdp[23:16] 1 (lower byte) mdqmp 1 mdp[15:8] 0 (upper byte) mdqmp 0 mdp[7:0] 0 (lower byte
minirisc MR4010 superscalar microprocessor 29 lcresetn lclk divider reset input you can use this input for testing. normally you should strap it high (deasserted) on the system board, which means the signal is deasserted. lchalfn lbus clock speed input this signal sets the clock speed for the lbus. when a device on the lbus drives this signal low, it divides the scbus clock (sclkp) by two and the MR4010 outputs a clock signal (lclkp) that is half the frequency of sclkp. when the signal is high, it divides the clock by four, and the MR4010 outputs a clock signal (lclkp) that is one quarter the frequency of sclkp. lclkp lbus clock output this output is derived from the scbus clock, sclkp. the lbus clock rate is either half or quarter the clock rate of sclkp, depending on the state of the lchalfn input to the MR4010. lap[31:2] lbus address bus bidirectional when the MR4010 is master of the lbus, it outputs the address that is used to access one of the devices on the lbus. if one of the devices on the lbus is bus master, it inputs the address that the MR4010 uses to access the dram. ldp[31:0] lbus data bus bidirectional this 32-bit bidirectional data bus transfers data between the devices on the lbus and the MR4010. the read/write signal, lrdn , controls the direction of data ?ow on the lbus. lben[3:0] lbus byte enables bidirectional when the master device drives these signals active (low), they enable data on the lbus, as shown below. the read/write signal, lrdn, controls the direction of data ?ow. byte enable signal byte bits byte number lben 3 ldp[31:24] byte 3 lben 2 ldp[23:16] byte 2 lben 1 ldp[15:8] byte 1 lben 0 ldp[7:0] byte 0
30 minirisc MR4010 superscalar microprocessor lrdn lbus read bidirectional the master device asserts this signal to enable a read operation and deasserts it to enable a write operation. when the MR4010 asserts lhldap and grants bus own- ership to an lbus master device, the master device inputs this signal to the MR4010. when the MR4010 is the bus master, it inputs this signal to the lbus device. the initi- ating device must synchronize this signal to the lbus clock, lclkp. ladsn lbus address strobe bidirectional this signal strobes the lbus addresses. the bus master asserts it at the ?rst lclkp cycle of a transaction. when the MR4010 asserts lhldap and grants bus ownership to an lbus master device, the master device inputs this signal to the MR4010. when the MR4010 is the bus master, it inputs this signal to the lbus device. the initi- ating device must synchronize this signal to the lbus clock, lclkp. lrdyn lbus data ready bidirectional when it is asserted, this signal terminates a transaction. when the MR4010 asserts lhldap and grants bus own- ership to an lbus master device, the master device inputs this signal to the MR4010. when the MR4010 is the bus master, it inputs this signal to the lbus device. the initi- ating device must synchronize this signal to the lbus clock, lclkp lrtyn lbus retry input when an lbus master device asserts this signal and inputs it to the MR4010, the MR4010 temporarily aborts any transaction in progress and initiates the transaction again later. the initiating lbus device must synchronize the signal to the rising edge of lclkp. lholdp lbus hold request input an lbus device asserts lholdp to request ownership of the lbus. the initiating device must synchronize the signal to the rising edge of lclkp.
minirisc MR4010 superscalar microprocessor 31 lhldap lbus hold acknowledge output the MR4010 asserts this signal in response to an lholdp input from an lbus device. when asserted, the signal grants a bus hold and allows the lbus device to take bus ownership. 4.6 phase-locked loop (pll) clock signals the pll circuit generates the clock inputs for the cw4010 shell and for the other modules that are part of the MR4010. the pll is part of the MR4010 reference device, as shown in figure 1 on page 7 . this section describes the pll signals. pll circuit, on page 36 provides further information. the test signals associated with the pll circuit are not for general use and are therefore deasserted by strapping them low if they are active-high signals, and strapping them high if they are active-low signals. pllrefp system clock reference input this is the system reference clock, input to the cw4010 by the pll circuit. pllenp vco enable(1)/disable(0) strapped input this signal is input to the pll circuit and enables the pll circuit when it is active (high). it is strapped high on the main circuit board so that the pll circuit is always enabled. plllp2p vco input and loop filter filter pin you must connect an rc (resistor/capacitor) circuit for the pll ?lter between pins plllp2p and pllagnd on the pll circuit, as shown in figure 11 ,on page 36 . plliddtp test enable input input to pll circuit this signal enables test inputs when it is active (high). it is strapped low on the main circuit board. pllctop test counter open output from pll circuit this signal is an open pin on the board. pllctrn test counter reset input to pll circuit this signal is strapped low on the board. plltstp test enable input to pll circuit this signal is strapped low on the board, which means that testing is generally disabled.
32 minirisc MR4010 superscalar microprocessor plltdp test data (clock) input to pll circuit this signal is strapped low on the board. pllvdd pll power input to pll circuit this signal provides vdd power. pllvss pll ground ground this is the ground for the pll circuit. pllagnd pll analog ground ground this is the analog ground for the pll circuit. you must connect an rc (resistor/capacitor) circuit for the pll ?lter between pins plllp2p and pllagnd on the pll circuit, as shown in figure 11 on page 36 . test signals there are nine pins on the MR4010 chip that allow designers at lsi logic to test devices on the board using an lsi tester. when the pins are not being used for testing, you must deassert all inputs by strapping active-high signals low and active-low signals high. you must leave all outputs open. inputs and outputs are referenced to and from the MR4010. scancrip cw4010 core scan input this input allows you to initiate a scan of the cw4010 core. strap it low on the board. scancrop cw4010 core scan output this output allows you to read the results of the cw4010 core scan. leave it open on the board. scankzip MR4010 peripherals scan input this input allows you to initiate a scan of the peripheral circuitry that is part of the MR4010 reference device. strap it low on the board. scankzop MR4010 peripherals scan output this output allows you to read the results of the MR4010 peripherals scan. leave it open on the board. scanenbp global MR4010 scan enable input this input allows you to initiate a global scan of the MR4010. strap it low on the board.
minirisc MR4010 superscalar microprocessor 33 scanmonp scan mode monitor output this output allows you to monitor the scan mode. leave it open on the board. zstaten global 3-state control input this input is reserved for factory use during testing . strap it high on the board. paramoutp parametric nand tree output this output allows you to check the parametric nand tree. it is reserved for factory use during testing. leave it open on the board. testmp test mode for scan input this input is reserved for factory use during testing . strap it low on the board through a 10 k resistor. 4.7 cw4010 core monitor signals there are 11 pins that enable you to monitor the behavior of the cw4010 core. when you are not using the outputs to monitor the core, make sure they are open. brlikfn cw4010 branchlikely of even slot is false output the cw4010 asserts brlikfn when the branch likely instruction is in an even slot and it is false. if, at this time, a coprocessor has a valid instruction in the ex stage, the instruction must be cancelled. it is not necessary to check whether the instruction in the ex stage is in an even or odd slot, since the cw4010 asserts brlikfn only when the branch likely instruction is in the even slot. if the branch likely instruction in the even slot is not taken, the instruction in the odd slot must be nulli?ed although it has already been started. mclkp internal clock monitor output this output from the internal clock allows you to check the clock phase. when you are not using the pin to check the clock, the output should be open. pcancrn cw4010 pipeline cancel at cr stage output when one or more exceptions occur, the pipeline is cancelled at the cr stage and the cw4010 asserts pcancrn. coprocessor pipelines must be cancelled to prevent a second execution of the coprocessor instruction under either of the following conditions: when the copro- cessor returns from an exception handler; or when the
34 minirisc MR4010 superscalar microprocessor coprocessor has ?nished executing an lwcz instruction that caused a tlb (translation lookaside buffer) miss. the wb stage is not cancelled when pcancrn is asserted. pcanoddn cw4010 pipeline cancel to odd output pcanoddn is valid only when pcancrn is asserted. the signal informs coprocessors whether the cancellation is for an odd or even slot. when the cw4010 asserts the signal, cancellation applies to the odd slot. when it deas- serts the signal, cancellation applies to both even and odd slots. the coprocessor must track which slot it is executing in based on the cpxoddn signal. when the cw4010 asserts both pcancrn and pcanoddn and the coprocessor instruction is in the odd slot, the instruction must be cancelled. when the cw4010 asserts pcancrn and deasserts pcanoddn, the coprocessor instruction must be cancelled regardless of the slot in which it is operating. this signal is valid at the cr stage of the pipeline. pstalln cw4010 pipeline stall monitor output the cw4010 asserts this signal to indicate that all stages of the cw4010 pipelines are stalled. pipelines must be stalled when they are executing instructions. this signal is valid at any stage of the pipelines. scaoen scbus address output enable output the cw4010 asserts sca0en to indicate that the address output bus scaop[31:0] lines are valid. the cw4010 asserts the signal when the biu is performing an scbus transaction, and the signal remains active throughout the operation. scbrdyn scbus bus ready output the sclc asserts scbrdyn when the current transac- tion is terminated. when asserted, it indicates that the scbus is available. the signal remains active (low) until the next transaction starts. the sclc then deasserts the signal to indicate that the scbus is not available.
minirisc MR4010 superscalar microprocessor 35 scdoen scbus data output enable output the cw4010 asserts scdoen to indicate that the data output signals scdop[63:0] are valid. the cw4010 asserts the signal throughout the write transaction to indicate that the current transaction is a write transaction and to enable data output. scifetn scbus instruction fetch output sscifetn indicates that the biu is fetching an instruction for monitoring purposes. the cw4010 drives the signal low at this time and outputs it to external logic. sctbstn scbus burst transaction output the cw4010 uses burst transactions to the dram con- troller. when the cw4010 asserts sctbstn, it indicates that a dram transaction is taking place during which four doublewords will be moved, and that currently the ?rst doubleword is being moved. the cw4010 deasserts the signal after the ?rst word has been transferred and during singleword transactions. sctssn scbus transaction start strobe output when the cw4010 asserts sctssn, it indicates that a transaction has started. the cw4010 asserts the signal for one clock cycle at the beginning of a transaction. if the transaction lasts through one cycle and the next transac- tion begins immediately, the cw4010 asserts sctssn continuously. suspexn cw4010 suspend ex stage output the cw4010 instruction scheduler unit (isu) asserts suspexn to request coprocessors to suspend the instruction in the ex stage. the instruction in the ex stage must be held until the isu deasserts suspexn. instructions in the cr and wb stages must be completed. this signal is valid at the ex stage of the pipeline.
36 minirisc MR4010 superscalar microprocessor 5 pll circuit figure 11 shows the layout of the MR4010 pll circuit. this circuit is an lsi logic pll cell (pll5080cb) used for cell-based design. the system clock drives the pllrefp input. you need to provide capacitance devices and a resistor between plllp2p and pllagnd. you must connect other pll circuit inputs to vdd or gnd. scanmonp and pllctop outputs must be open. for more information about the pll circuit, refer to the lsi logic lcb500k preliminary design manual . figure 11 MR4010 pll circuit diagram pllenp pllrefp pllvdd pllvss plliddtp plltdp plltstp az (&ibuf) az (&ddrv..no pi&po) az (pllvdd..no pi&po) az (pllvss..no pi&po) az (&iiddtn) pllvss az (&ibuf) az (&ibuf) az (&ibuf) pllctrn 10-bit iddtn a cs z (mux31hc) plllp2p pllagnd az (&ddrv..no pi&po) c r c1 io a en (plllp2.."io" is de?ned to both in and out) (clkc16i) a z a z (clkc16i) sclkp nbsclkp pllvdd fb ref lp2 ckout ckoutp xlp2p xpllrefp xpllvdd xpllvss xplliddtn xplltdp xplltstp xpllctrn pllctop az (&b1) xpllctop xpllenn xpllagnd...alias (pll5080cb or pll5080ga) scanmonp az (&b1) cp cd ctop (20 pf) (0.001uf) (200ohm) (active high) b (bufa) scanreqp from debug unit (cp0) 01 ld4qa fd2qa fd2qa cold reset cd cd cd (or2a) 3:1 multiplexer counter
minirisc MR4010 superscalar microprocessor 37 6 system con?guration MR4010 has a number of features that allow you to modify the system con?guration. this section describes the con?guration and cache control (ccc) register, which is part of the cw4010 core, and several lbus registers, which are part of the sclc module. you can also con?gure the dram, as described in dram modes and programmable con?gurations on page 59 . 6.1 cw4010 ccc register the con?guration and cache control (ccc) register is part of the cw4010 coprocessor, cp0. it allows you to use software to con?gure various pieces of the core design, such as the biu, the tlb, and the con- trollers for the icache and dcache. you can read from the ccc register or write to it using the mfc0 and mtc0 instructions described in ta b l e 2 , which starts on page 44 . the registers address in cp0 is 16. figure 12 shows the bit con?guration of the ccc register. all bits are initialized to 0 at reset, so that the caches are not available until the register is programmed. figure 12 cw4010 ccc register r reserved [31:28] this ?eld is reserved. the bits are cleared to 0. sdb scan debug 27 this bit enables the scan debug mode. setting the bit to 1 enables the mode and clearing it to 0 disables the mode. 31 28 27 26 25 24 23 22 21 20 19 18 17 16 r sdb ir1 evi cmp iie die mul mad tmr bge ie0 ie1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 is[1:0] de0 de1 ds[1:0] ipwe ipws[1:0] te wb sr0 sr1 isc tag inv md96.269
38 minirisc MR4010 superscalar microprocessor ir1 icache scratchpad ram 26 this bit enables set-1 of the icache to be used as scratchpad ram. setting the bit to 1 enables scratchpad ram mode. clearing it to 0 disables scratchpad ram mode. evi external vectored interrupt 25 this bit enables and disables external vectored interrupt. setting the bit to 1 enables the interrupt and clearing it to 0 disables the interrupt. cmp r3000 compatibility 24 this bit enables and disables r3000 compatibility mode. setting the bit to 1 enables the mode and clearing it to 0 disables the mode. iie icache invalidate enable 23 this bit enables and disables the icache invalidate request. setting the bit to 1 enables the request and clearing it to 0 disables the request. die dcache invalidate enable 22 this bit enables and disables the dcache invalidate request. setting the bit to 1 enables the request and clearing the bit to 0 disables the request. mul multiplier 21 this bit enables and disables the hardware multiplier. setting the bit to 1 enables the multiplier and clearing the bit to 0 disables the multiplier. mad multiply accumulate 20 this bit allows the multiplier to support accumulate exten- sions. setting the bit to 1 enables the feature and clearing the bit disables the feature. when this bit is set, mul must also be set. tmr timer 19 setting this bit to 1 enables the timer facility associated with the cw4010 cores count and compare registers. when this bit is set, and the value of the count register equals the value of the compare register, interrupt bit ip7 in the cause register is set. ip7 causes an interrupt in the next execution cycle, provided that interrupts are enabled by setting the interrupt enable bit in the mode
minirisc MR4010 superscalar microprocessor 39 register to 1 and clearing the error level and exception level bits in the mode register to 0. bge biu bus enable grant 18 this bit enables and disables the biu bus grant. setting this bit to 1 enables the external bus master. clearing it to 0 allows the cw4010 core to ignore the external bus master. ie0 icache set-0 enable 17 this bit enables and disables set-0 of the icache. setting the bit to 1 enables set-0 and clearing it to 0 disables set-0. ie1 icache set-1 enable 16 this bit enables and disables set-1 of the icache. setting the bit to 1 enables set-1 and clearing it to 0 disables set-1. is[1:0] icache size [15:14] the is[1:0] ?eld determines the size of each icache set. the ?eld settings are de?ned as follows: de0 dcache set-0 enable 13 this bit enables and disables set-0 of the dcache. setting the bit to 1 enables set-0 and clearing it to 0 disables set-0. de1 dcache set-1 enable 12 this bit enables and disables set-1 of the dcache. setting the bit to 1 enables set-1 and clearing it to 0 disables set-1. is1 is0 cache set size 0 0 1 kbyte 0 1 2 kbyte 1 0 4 kbyte 1 1 8 kbyte
40 minirisc MR4010 superscalar microprocessor ds[1:0] dcache size [15:14] the ds[1:0] ?eld determines the size of each dcache set. the ?eld settings are de?ned as follows: ipwe in-page write enable 9 this bit enables and disables in-page write operations. setting the bit to 1 enables in-page write and clearing it to 0 disables in-page write. ipws[1:0] in-page write size [8:7] the ipws[1:0] ?eld determines the size of the icache set. the ?eld settings are de?ned as follows: te tlb enable 6 this bit enables and disables the tlb. setting the bit to 1 enables the tlb and clearing the bit to 0 disables the tlb. wb writeback 5 this bit de?nes operation for addresses not mapped by the tlb. setting the bit to 1 enables a writeback opera- tion and clearing it to 0 enables a writethrough operation. sr0 scratchpad ram mode set-0 4 this bit enables and disables scratchpad ram mode for set-0 of the dcache. setting the bit to 1 enables scratch- pad mode and clearing it to 0 disables scratchpad mode. ds1 ds0 cache set size 0 0 1 kbyte 0 1 2 kbyte 1 0 4 kbyte 1 1 8 kbyte ipws1 ipws0 in-page write size 0 0 1 kbyte 0 1 2 kbyte 1 0 4 kbyte 1 1 8 kbyte
minirisc MR4010 superscalar microprocessor 41 sr1 scratchpad ram mode set-1 3 this bit enables and disables scratchpad ram mode for set-1 of the dcache. setting the bit to 1 enables scratch- pad mode and clearing it to 0 disables scratchpad mode. isc isolate cache 2 this bit enables isolate cache mode. this means that stores to the cache are not propagated to external memory. setting the bit to 1 enables the mode and clearing it to 0 disables the mode. tag tag test mode 1 this bit enables and disables tag test mode, which is used for cache maintenance. setting the bit to 1 enables the mode, which means that load and store operations access the tag rams, and sample the tag bits tag data, hit, writeback (dcache only), and valid. clearing the bit to 0 disables tag test mode. inv invalidate cache mode 0 this bit enables and disables cache invalidate mode, which is used for cache maintenance. setting the bit to 1 enables the mode, which means that the software must invalidate all lines in the icache and the dcache. after reset, zeros must be written into all tags for both sets of the icache and dcache. clearing the bit to 0 disables invalidate cache mode. 6.2 lbus controller registers the lbus controller has three 32-bit registers that store information about scbus errors and interrupts. they are the scbus error address register, the scbus error status register, and the external vectored interrupt register: you must access these registers through kseg1 . access to an unused address causes an scbus timeout error. ta bl e 1 shows the phys-
42 minirisc MR4010 superscalar microprocessor ical and virtual addresses of these registers. scbus timeout watchdog timer on page 85 provides further information on this subject. 7 MR4010 memory map figure 13 shows the memory map of the MR4010 where the MR4010 is bus master, and where an lbus device is bus master and the MR4010 is a slave. in both cases, address spaces are linear 4-gbyte spaces. lbus master devices cannot access MR4010 internal memory mapped registers. synchronous dram main memory that is interfaced to the MR4010 is located at address space 0x0000 0000 through 0x03ff ffff. the MR4010 works as an lbus slave device for this 64-mbyte memory space. there is no guarantee that memory devices exist in the entire 64-mbyte area. software, in the form of a setup/bootstrap utility or equiv- alent, must check installed memory size when the system is initialized. the upper 192-mbyte space is reserved as an extended main memory area. MR4010 internal registers for dram controller and error reporting are located in the internal registers area between addresses 0x1000 0000 and 0x10ff ffff. these registers must be accessed through kseg1 , the uncached-unmapped area. the virtual address for these registers is 0xb000 0000 through 0xb0ff ffff. ta b l e 1 bus error internal registers name virtual address physical address function scbus error address register 0x b010 0000 0x 1010 0000 contains the scbus error address scbus error status register 0x b010 0004 0x 1010 0004 contains the error status information for the scbus external vectored interrupt register 0x b010 0008 0x 1010 0008 contains the vectored interrupt for the scbus
minirisc MR4010 superscalar microprocessor 43 figure 13 MR4010 master/slave memory map 8 cw4010 instruction set summary ta b l e 2 describes the instructions that make up the MR4010 instruction set. the chip supports 32-bit mips-ii instructions and also implements additional extended instructions. the instructions are arranged alphabet- ically within the following functional groups: load and store, on page 44 load linked, on page 45 alu immediate, on page 45 alu three-operand register type, on page 46 shift, on page 47 multiply/divide, on page 48 cw4010 extended computational, on page 48 jump, on page 50 branch, on page 50 trap, on page 52 special, on page 52 0x0000 0000 0x0400 0000 0x1000 0000 0xffff ffff lbus access area internal register area MR4010 master address map 0x1100 0000 0x1fc0 0000 MR4010 slave address map 0x0000 0000 0x0400 0000 0x1000 0000 0xffff ffff lbus access area unusable area 0x1100 0000 0x1fc0 0000 highest order address lowest order address md96.270 reserved main memory area reserved main memory area dram main memory area dram main memory area
44 minirisc MR4010 superscalar microprocessor coprocessor, on page 52 cp0, on page 53 cache maintenance, on page 54 ta b l e 2 MR4010 (cw4010) instruction set summary instruction format and description load and store instructions load byte lb rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. sign-extend the contents of addressed byte and load into rt . load byte unsigned lbu rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. zero-extend the contents of addressed byte and load into rt . load halfword lh rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. sign-extend the contents of addressed halfword and load into rt . load halfword unsigned lhu rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. zero-extend contents of addressed halfword and load into rt . load word lw rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address, and load the addressed word into rt . load word left lwl rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift addressed word left so that addressed byte is leftmost byte of a word. merge bytes from memory with contents of register rt and load result into register rt . load word right lwr rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift addressed word right so that addressed byte is rightmost byte of a word. merge bytes from memory with contents of register rt and load result into register rt . store byte sb rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. store least-signi?cant byte of register rt at addressed location. (sheet 1 of 11)
minirisc MR4010 superscalar microprocessor 45 load and store instructions (continued) store halfword sh rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. store least-signi?cant halfword of register rt at addressed location. store word sw rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. store contents of register rt at addressed location. store word left swl rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift contents of register rt left so that the leftmost byte of the word is in the position of the addressed byte. store word containing shifted bytes into word at addressed byte. store word right swr rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift contents of register rt right so that the rightmost byte of the word is in the position of the addressed byte. store word containing shifted bytes into word at addressed byte. load linked instructions load linked ll rt, offset(base) sign extend the 16-bit offset and add to the contents of the register base to form the address. load the addressed word into register rt . store conditional sc rt, offset(base) sign extend the 16-bit offset and add to the contents of the register base to form the address. conditionally store register rt at the address, based on whether the load-link has been broken. synchronize sync complete all outstanding load and store instructions before allowing any new load or store instruction to start. alu immediate instructions add immediate addi rt, rs, immediate add 16-bit, sign-extended immediate to register rs and place 32-bit result in register rt . trap on twos complement over?ow. add immediate unsigned addiu rt, rs, immediate add 16-bit, sign-extended immediate to register rs and place 32-bit result in register rt . do not trap on over?ow. table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 2 of 11)
46 minirisc MR4010 superscalar microprocessor alu immediate instructions (continued) set on less than immediate slti rt, rs, immediate compare 16-bit, sign-extended immediate with register rs as signed 32-bit integers. result = 1 if rs is less than immediate; otherwise result = 0. place result in register rt . set on less than immediate unsigned sltiu rt, rs, immediate compare 16-bit, sign-extended immediate with register rs as unsigned 32-bit integers. result = 1 if rs is less than immediate ; otherwise result = 0. place result in register rt . and immediate andi rt, rs, immediate zero-extend 16-bit immediate , and with contents of register rs , and place result in register rt . or immediate ori rt, rs, immediate zero-extend 16-bit immediate , or with contents of register rs , and place result in register rt . exclusive or immediate xori rt, rs, immediate zero-extend 16-bit immediate , exclusive or with contents of register rs , and place result in register rt . load upper immediate lui rt, immediate shift 16-bit immediate left 16 bits. set least-signi?cant 16 bits of word to zeros. store result in register rt . alu three-operand register type instructions add add rd, rs, rt add contents of registers rs and rt and place 32-bit result in register rd . trap on twos complement over?ow. add unsigned addu rd, rs, rt add contents of registers rs and rt and place 32-bit result in register rd . do not trap on over?ow. subtract sub rd, rs, rt subtract contents of registers rt from rs and place 32-bit result in register rd . trap on twos complement over?ow. subtract unsigned subu rd, rs, rt subtract contents of register rt from rs and place 32-bit result in register rd . do not trap on over?ow. set on less than slt rd, rs, rt compare contents of registers rt and rs (as signed, 32-bit integers). if register rs is less than rt , rd = 1; otherwise, rd =0. table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 3 of 11)
minirisc MR4010 superscalar microprocessor 47 alu three-operand register type instructions (continued) set on less than unsigned sltu rd, rs, rt compare contents of registers rt and rs (as unsigned, 32-bit integers). if register rs is less than rt , rd = 1; otherwise, rd =0. and and rd, rs, rt bitwise and contents of registers rs and rt and place result in register rd . or or rd, rs, rt bitwise or contents of registers rs and rt and place result in register rd . exclusive or xor rd, rs, rt bitwise exclusive or contents of registers rs and rt and place result in register rd . nor nor rd, rs, rt bitwise nor contents of registers rs and rt and place result in register rd . shift instructions shift left logical sll rd, rt, shamt shift contents of register rt left by shamt bits, inserting zeros into low-order bits. place 32-bit result in register rd . shift right logical srl rd, rt, shamt shift contents of register rt right by shamt bits, inserting zeros into high-order bits. place 32-bit result in register rd . shift right arithmetic sra, rd, rt, shamt shift contents of register rt right by shamt bits, sign-extending the high-order bits. place 32-bit result in register rd . shift left logical variable sllv rd, rt, rs shift contents of register rt left. low-order 5 bits of register rs specify the number of bits to shift. insert zeros into low-order bits of rt and place 32-bit result in register rd . shift right logical variable srlv rd, rt, rs shift contents of register rt right. low-order 5 bits of register rs specify the number of bits to shift. insert zeros into high-order bits of rt and place 32-bit result in register rd . shift right arithmetic variable srav rd, rt, rs shift contents of register rt right. low-order 5 bits of register rs specify the number of bits to shift. sign-extend the high-order bits of rt and place 32-bit result in register rd . table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 4 of 11)
48 minirisc MR4010 superscalar microprocessor multiply/divide instructions multiply mult rs, rt multiply contents of registers rs and rt as twos complement values. place the 64-bit results in special registers entryhi and entrylo . (the entrylo and entryhi registers are read/write registers that access the tlb.) multiply unsigned multu rs, rt multiply contents of registers rs and rt as unsigned values. place 64-bit results in special registers entryhi and entrylo. divide div rs, rt divide contents of registers rs by the contents of rt as twos complement values. place the 32-bit quotient in special register entrylo and the 32-bit remainder in entryhi. divide unsigned divu rs, rt divide contents of registers rs by the contents of rt as unsigned values. place the 32-bit quotient in special register entrylo and the 32-bit remainder in entryhi. move from hi mfhi rd move contents of special register entryhi to register rd . move from lo mflo rd move contents of special register entrylo to register rd . move to hi mthi rs move contents of register rs to special register entryhi. move to lo mtlo rs move contents of register rd to special register entrylo. cw4010 extended computational instructions add circular immediate addciu rt, rs, immediate the 16-bit immediate is sign extended and added to the contents of general register rs , with the result masked by the value in cp0s cmask register according to the formula: rt = (rs 31...cmask ||(rs+signextended_imed) cmask-1...0) find first set bit ffs rd, rs starting at the most signi?cant bit in register rs , ?nd the ?rst bit which is set to 1, and return the bit number in register rd . if no bit is set, return with all bits of rd set to 1. find first clear bit ffc rd, rs starting at the most signi?cant bit in register rs , ?nd the ?rst bit which is set to 0, and return the bit number in register rd . if no bit is set, return with all bits of rd set to 1. table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 5 of 11)
minirisc MR4010 superscalar microprocessor 49 cw4010 extended computational instructions (continued) select and shift right selsr rd, rs, rt using register rs and rt as a 64-bit register pair, and the contents of the cp0s rotate register as the shift count, shift the register pair rs || rt right the number of bits speci?ed in the rotate register, and place the least signi?cant 32-bit value in result register rd . select and shift left selsl rd, rs, rt using register rs and rt as a 64-bit register pair, and the contents of the cp0s rotate register as the shift count, shift the register pair rs || rt left the number of bits speci?ed in the rotate register, and place the most signi?- cant 32-bit value in result register rd . multiply/add madd rs, rt multiply contents of registers rs and rt as twos complement values. add 64-bit results to the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. (the entrylo and entryhi registers are read/write registers that access the tlb.) multiply/add unsigned maddu rs, rt multiply contents of registers rs and rt as unsigned values. add 64-bit results to the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. multiply/subtract msub rs, rt multiply contents of registers rs and rt as twos complement values. sub- tract the 64-bit results from the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. multiply/subtract unsigned msubu rs, rt multiply contents of registers rs and rt as unsigned values. subtract the 64-bit results from the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. minimum min rd, rs, rt compare the contents of registers rs and rt as twos complement values. the smaller value is stored in register rd . maximum max rd, rs, rt compare the contents of registers rs and rt as twos complement values. the larger value is stored in register rd . table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 6 of 11)
50 minirisc MR4010 superscalar microprocessor jump instructions jump j target shift 26-bit target address left two bits, combine with four high-order bits of pc, and jump to address with a one-instruction delay. jump and link jal target shift 26-bit target address left two bits, combine with four high-order bits of pc, and jump to address with a one-instruction delay. place address of instruction following delay slot in r31 (link register). jump register jr rs jump to address contained in register rs with a one-instruction delay. jump and link register jalr rs, rd jump to address contained in register rs with a one-instruction delay. place address of instruction following delay slot in rd . branch instructions branch on equal beq rs, rt, offset branch to target address if register rs is equal to register rt . (see footnote 1 at the end of the table.) branch on not equal bne rs, rt, offset branch to target address if register rs does not equal register rt . branch on less than or equal to zero blez rs, offset branch to target address if register rs is less than or equal to 0. branch on greater than zero bgtz rs, offset branch to target address if register rs is greater than 0. branch on less than zero bltz rs, offset branch to target address if register rs is less than 0. branch on greater than or equal to zero bgez rs, offset branch to target address if register rs is greater than or equal to 0. branch on less than zero and link bltzal rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is less than 0. branch on greater than or equal to zero and link bgezal rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is greater than or equal to 0. branch on equal likely beql rs, rt, offset branch to target address if register rs is equal to register rt . branch on not equal likely bnel rs, rt, offset branch to target address if register rs does not equal register rt . table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 7 of 11)
minirisc MR4010 superscalar microprocessor 51 branch instructions (continued) branch on less than or equal to zero likely blezl rs, offset branch to target address if register rs is less than or equal to 0. branch on greater than zero likely bgtzl rs, offset branch to target address if register rs is greater than 0. branch on less than zero likely bltzl rs, offset branch to target address if register rs is less than 0. branch on greater than or equal to zero likely bgezl rs, offset branch to target address if register rs is greater than or equal to 0. branch on less than zero and link likely bltzall rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is less than 0. branch on greater than or equal to zero and link likely bgezall rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is greater than or equal to 0. trap instructions trap on equal teq rs, rt trap if register rs is equal to register rt . trap on equal immediate teqi rs, immediate trap if register rs is equal to the immediate value. trap on greater than or equal tge rs, rt trap if register rs is greater than or equal to register rt . trap on greater than or equal immediate tgei rs, immediate trap if register rs is greater than or equal to the immediate value. trap on greater than or equal unsigned tgeu rs, rt trap if register rs is greater than or equal to register rt . trap on greater than or equal immediate unsigned tgeiu rs, immediate trap if register rs is greater than or equal to the immediate value. trap on less than tlt rs, rt trap if register rs is less than register rt . trap on less than immediate tlti rs, immediate trap if register rs is less than the immediate value. trap on less than unsigned tltu rs, rt trap if register rs is less than register rt . table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 8 of 11)
52 minirisc MR4010 superscalar microprocessor trap instructions (continued) trap on less than immediate unsigned tltiu rs, immediate trap if register rs is less than the immediate value. trap if not equal tne rs, rt trap if register rs is not equal to rt . trap if not equal immediate tnei rs, immediate trap if register rs is not equal to the immediate value. special instructions system call syscall initiate system call trap, immediately transferring control to exception handler. breakpoint break initiate breakpoint trap, immediately transferring control to exception handler. coprocessor instructions load word to coprocessor lwcz rt, offset(base) extend the sign of the 16-bit offset and add the offset to the contents of the general register base to form a 32-bit unsigned effective address. the word at the memory location speci?ed is loaded into coprocessor register rt of the coprocessor unit z. store word from coprocessor swcz rt, offset(base) extend the sign of the 16-bit offset and add the offset to the contents of the general register base to form a 32-bit unsigned effective address. the contents of coprocessor register rt of the coprocessor unit z are stored at the address speci?ed by the 32-bit unsigned effective address. move to coprocessor mtcz rt, rd load the contents of general register rt into the rd register of coprocessor unit z. move from coprocessor mfcz rt, rd load the contents of the rd register of coprocessor unit z into general register rt . move control to coprocessor ctcz rt, rd load the contents of general register rt into the control register rd of copro- cessor unit z. move control from coprocessor cfcz rt, rd load the contents of the control register rd of coprocessor unit z into general register rt . table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 9 of 11)
minirisc MR4010 superscalar microprocessor 53 coprocessor instructions (continued) coprocessor operation copz cofun initiate a coprocessor operation that may specify and reference the copro- cessors internal registers or change the state of the coprocessors condition line, but does not change the state within the processor or the cache memory. branch on coprocessor z true (likely) bczt offset, (bcztl offset) compute a branch target address by adding address of instruction to the 16-bit offset (shifted left two bits and sign-extended to 32 bits). branch to the target address (with a delay of one instruction) if coprocessor zs condi- tion line is true. in a branch likely, the delay slot instruction is not executed when the branch is not taken. branch on coprocessor z false (likely) bczf offset, (bczfl offset) compute a branch target address by adding address of instruction to the 16-bit offset (shifted left two bits and sign-extended to 32 bits). branch to the target address (with a delay of one instruction) if coprocessor zs condi- tion line is false. in a branch likely, the delay slot instruction is not executed when the branch is not taken. cp0 instructions move to cp0 mtc0 rt, rd load contents of cpu register rt into cp0 register rd . move from cp0 mfc0 rt, rd load contents of cp0 register rd into cpu register rt . read indexed tlb entry tlbr load the entryhi and entrylo registers with the tlb entry pointed to by the index register. write indexed tlb entry tlbwi load tlb entry pointed to by the index register with the contents of the entryhi and entrylo registers. write random tlb entry tlbwr load tlb entry pointed to by the random register with the contents of the entryhi and entrylo registers. probe tlb for matching entry tlbp load the index register with the address of the tlb entry whose contents match the entryhi and entrylo registers. if no tlb entry matches, set the high-order bit of the index register. table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 10 of 11)
54 minirisc MR4010 superscalar microprocessor cp0 instructions (continued) exception return 2 eret (r4000 mode) load the pc from errorepc(sr2=1:error exception) or epc(sr2=0:exception) and clear erl bit (sr2=1) or exl bit (sr2=0) in the status register. sr2 is status register bit[2]. restore from exception 2 rfe (r3000 mode) restore previous interrupt mask and mode bits of the status register into current status bits. restore old status bits into previous status bits. wait for interrupt waiti stop execution of instructions and places the processor into a power save (stall) condition until a hardware interrupt, nmi (nonmaskable interrupt), or reset is received. cache maintenance instructions flush icache flushi flush icache. 256 stall cycles will be needed. flush dcache flushd flush dcache. 256 stall cycles will be needed. flush icache & dcache flushid flush both icache and dcache in 256 stall cycles. writeback wb offset(base) write back a dcache line addressed by offset+gpr[base]. this instruction applies to both dcache sets. 1. all branch-instruction target addresses are computed as follows: add the address of instruction in the delay slot and the 16-bit offset (shifted left two bits and sign-extended to 32 bits). all branches occur with a delay of one instruction. 2. these two instructions cannot both be legal at the same time. the one that is not legal causes a reserved instruction exception. table 2 (cont.) MR4010 (cw4010) instruction set summary instruction format and description (sheet 11 of 11)
minirisc MR4010 superscalar microprocessor 55 9 dram controller and memory bus this section describes the synchronous dram controller and the memory bus. it de?nes: dram types compatible with the MR4010 address space available for the dram memory interface memory address bit assignment programmable features of the dram, including the dram mode register and dram controller con?guration register dram refresh requirements, and the dram controller refresh register and refresh counter dram commands initializing the dram timing requirements for the different dram transactions 9.1 dram types and available dram address area the MR4010 interfaces directly to synchronous drams without any glue logic through a 64-bit memory data bus. when the dram is arranged in two banks, the chip select signals mcsn[1:0] select between the two banks as described on page 26 .
56 minirisc MR4010 superscalar microprocessor ta b l e 3 shows different dram con?gurations and the address ranges assigned to the memory banks. there is no programmable feature that de?nes the dram size and con?guration. the utility setup/bootstrap program should check the amount of installed dram when the system is initially powered up. 9.2 memory interface figure 14 shows the interface between MR4010 mbus and the drams. in the example shown, eight 16-bit dram devices are arranged in two memory banks to provide 16 mbytes of memory. this is the con?guration shown in line 2 of ta b l e 3 . as shown in ta b l e 3 , this con?guration does not have continuous memory space. a clock delay tap provides the clock input for the drams. the clock enable (cke) inputs to the drams are tied high, which means that they are always asserted. the MR4010 selects between bank 0 and bank 1 of the dram by means of the chip select signals, mcsn[1:0]. it asserts mcsn0 to select the four drams in bank 0, and mcsn1 to select the four drams in bank 1. the MR4010 distributes address (map[11:0]), row address strobe and column address strobe (mras and mcas) and the write enable signal (mwen) to all drams. data (mdp[63:0]) and the data mask (mdqmp[7:0]) are distributed to each byte in the dram array, with mdqmp7 masking byte 7 (bits [63:56]), and so forth. ta b l e 3 dram con?gurations dram type number of banks number of drams memory size cs0 bank area address range cs1 bank area address range 1 mbyte x 16 1 4 8 mbyte 0x0000 0000 C 0x007f ffff none 1 mbyte x 16 2 8 16 mbyte 0x0000 0000 C 0x007f ffff 0x0200 0000 C 0x027f ffff 2 mbyte x 8 1 8 16 mbyte 0x0000 0000 C 0x00ff ffff none 2 mbyte x 8 2 16 32 mbyte 0x0000 0000 C 0x00ff ffff 0x0200 0000 C 0x02ff ffff 4 mbyte x 4 1 16 32 mbyte 0x0000 0000 C 0x01ff ffff none 4 mbyte x 4 2 32 64 mbyte 0x0000 0000 C 0x01ff ffff 0x0200 0000 C 0x03ff ffff
minirisc MR4010 superscalar microprocessor 57 figure 14 MR4010 interface with dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x16 dram [7] [6] [5] [4] [3] [2] [1] [0] [63:48] [47:32] [31:16] [15:0] mdqmp[7:0] mdp[63:0] map[11:0] mrasn mcasn mwen mcsn[1] mcsn[0] sclkp clock delay tap system clock source MR4010 high bank 0 bank 1 md96.271 unused taps
58 minirisc MR4010 superscalar microprocessor 9.3 address bit assignment the dram controller in the MR4010 derives the dram addresses, map[11:0], from the 32 scbus address bits output by the bus master, which may be the cw4010 core or the sclc module. the controller outputs the address bits on the mbus, assigning the bits as shown in figure 15 . the byte select signals, mdqmp[7:0], are derived directly from the byte enable signals, sctben[7:0]. figure 15 scbus dram address bit assignment 0000 00 31 26 25 c9 cs c8 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 r0 24 23 22 21 20 19 18 17 16 15 14 13 12 11 c7 10 c6 9 c5 c4 8 7 c3 6 c2 5 c1 4 c0 3 000 2 0 x x x c8c7c6c5c4c3c2c1c0 scbus address bits x x c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 x x x x c7 c6 c5 c4 c3 c2 c1 c0 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 column addresses for 4-bit wide drams column addresses for 8-bit wide drams column addresses for 16-bit wide drams row addresses for all drams 109876543210 mbus address bits cs = 1 enables mcsn[1] to select bank 1 cs = 0 enables mcsn[0] to select bank 0 set to 0 set to 0 r9 r11 11 md96.272
minirisc MR4010 superscalar microprocessor 59 the map[11:0] 12-bit address bus multiplexes row and column addresses. ta b l e 4 lists the scbus address and mbus address bit assignments. 9.4 dram modes and programmable con?gurations the MR4010 dram controller supports a number of programmable modes. each dram has a mode register and the dram controller has a con?guration register. you can select different modes by setting the appropriate bits in the two registers. the modes you can program are: cache writethrough and writeback cache writethrough mode allows all data that is updated in the cache to be updated at the same time in external memory. in cache writeback mode, main memory is only updated when the cache line is reallocated or is explicitly ?ushed. burst length de?nes the number of words to be output or input during read and write cycles. in the MR4010, the burst length ?eld is set to 0. wrap type speci?es the order in which burst data is addressed. this mode does not apply in the MR4010, since the burst length ?eld is set to 0. ta b l e 4 scbus address and mbus address bit assignment scbus address bits address bit function mbus address bits sctben[7:0] byte selection during write operations mdqmp[7:0] scap[10:3] 1 column addresses c[7:0] map[7:0] scap[22:12] row addresses r[11:0] map[11:0] scap[24:23] column addresses c[9:8] map[9:8] scap[25] chip selection mcsn[1:0] scap[31:26] 2 not used not used 1. these bits are used for column addresses in 16-bit wide drams. they are used in conjunction with sc[23] for 8-bit wide drams, and with sc[24:23] for 4-bit wide drams. since sc[10:3] supply column addresses, the dram page size is 1 kbyte for all drams. 2. to access the dram, sc[31:26] must be set to 0. otherwise, the dram controller will not respond to an scbus transaction.
60 minirisc MR4010 superscalar microprocessor cas latency de?nes the number of clock cycles that must occur before data is available. auto precharge this mode is not used in the MR4010. 9.4.1 dram mode register figure 16 shows the format of the 12-bit dram mode register. this register is programmed by a mode write command. figure 16 dram mode register format when you power up the dram, the boot program precharges the dram devices. you should refer to the documentation supplied with the dram for further information on precharging. after precharge, you must program the mode register using the following procedure. step 1. before you program the mode registers, set the mrs bit in the dram controller con?guration register (see page 62 ). step 2. program the timing correctly. step 3. initiate a mode register write cycle by executing a write trans- action to one of the following addresses. the data stored should be all zeros. r reserved [11:10] [8:7] these bits are not used and are set to 0. 11 1098 76 432 0 r wb r cl wt bl md96.273 cas latency setting physical address virtual address 1 0x 0010 8000 0x a010 8000 2 0x 0011 0000 0x a011 0000 3 0x 0011 8000 0x a011 8000
minirisc MR4010 superscalar microprocessor 61 wb cache writethrough and writeback 9 you can select cache writethrough mode by setting this bit to 1. setting the bit to 0 selects writeback mode. however, there is no signi?cance to writethrough and writeback modes in MR4010 transactions, since the burst length is one word. cl cas latency [6:4] you can select among one-, two-, and three-cycle modes by programming bits [6:4] in the dram mode register. you should select one of the following settings (all other combinations of the bit settings are reserved): bits [21:20] in the dram controller con?guration regis- ter also select the cycle modes. you must set or clear the bits in both registers to select the required mode. wt wrap type 3 this mode is not used in the MR4010, so you should clear this bit to 0. setting the bit to 1 enables interleaved accesses; clearing it to 0 enables sequential accesses. since burst length is one word for the MR4010, wrap type has no meaning. sequential mode is compatible with scbus burst ordering. bl burst length [2:0] you can select single-cycle mode by clearing bits [2:0] of this register to 0b000. the sc bus requests four double- words as a burst block. with a data bus width of 64 bits, the MR4010 supports the request with multiple cas accesses. bit 6 bit 5 bit 4 cache latency modes 1 1. you must set the same cache latency mode in the dram controller con?guration regis- ter. 00 1 1 01 0 2 01 1 3
62 minirisc MR4010 superscalar microprocessor 9.4.2 dram controller con?guration register the dram controller con?guration register allows you to con?gure various features of the dram. the virtual and physical addresses for the register are shown below: figure 17 shows the format recommended for the dram controller con?guration register. figure 17 dram controller con?guration register format r reserved 31 [27:22] [19:18] 11 7 [3:2] these bits are not used and you should clear them to 0. pc precharge command 30 this bit enables the manual precharge command. if the cpu sets the bit to 1, the dram controller generates one precharge command cycle for both banks. the cpu sets the bit at power up. initialization clears the bit automatically. mrs mode register set 29 if the cpu sets the bit to 1, the subsequent store word operation to the dram area generates a mode register set command. the row address bits in the sc address bus (scbits [22:11]) select the addressed location during this type of operation. scbits[31:23] and scbits [10:0], which are the mode bits, must be set to 0. the cpu virtual address physical address 0x b000 0000 0x 1000 0000 31 30 29 28 27 22 21 20 19 18 17 16 r pc mrs ref r cl r rcd 15 12 11 10 8 7 6 4 3 2 1 0 rc r ras r dal r rp3 dpl2 md96.274
minirisc MR4010 superscalar microprocessor 63 clears the mrs bit when the word operation has been completed. ref refresh cycle 28 this bit enables the manual refresh cycle request (ref). if the cpu sets it to 1, one refresh cycle is generated for both memory banks. this bit is cleared automatically when the refresh cycle has been completed. you can also generate ref using the refresh counter, as described in dram refresh on page 67 . cl cas latency [21:20] you can set cas latency by programming the bits in this ?eld. you should select one of the following settings: although you can de?ne all dram timing parameters independently, as described in the surrounding para- graphs, cas latency de?nes relationship between other timing parameters. ta b l e 5 on page 67 shows the rela- tionships between cas latency, dram frequency, and other con?guration settings. you must also set the cas latency bits in the dram mode register to re?ect the same cas latency value. rcd active ras to read/write command period cycles [17:16] you can program the bits in this ?eld to select the number of active clock cycles for a read or write operation. you can select one of the following settings: bit 21 bit 20 cache latency cycles 01 1 10 2 11 3 bit 17 bit 16 active clock cycles 01 1 10 2 11 3
64 minirisc MR4010 superscalar microprocessor rc refresh to refresh/active command period cycles [15:12] this ?eld allows you to select the number of active read/write cycles between refresh cycles. you can program these bits as follows: ras active to precharge command period [10:8] this ?eld allows you to select the number of clock cycles that ras should stay active until the memory has been precharged. you can program the bits as follows: bit 15 bit 14 bit 13 bit 12 active read/write cycles 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 9 10 1 0 10 bit 10 bit 9 bit 8 active ras cycles 01 1 3 10 0 4 10 1 5 11 0 6 11 1 7
minirisc MR4010 superscalar microprocessor 65 dal data in to active/refresh command period [6:4] this ?eld allows you to select the number of active clock cycles between the time data input is valid until the refresh command is asserted. you can set the ?eld as follows: rp3 precharge to active command period 1 this bit allows you to select the number of active clock cycles in the period between precharge and an active read or write command. if you set the bit to 1, there are three clock cycles. if you clear the bit to 0, there are two clock cycles. dpl2 data in to precharge command period 0 this bit allows you to select the number of active clock cycles in the period between the input of valid data to the assertion of the precharge command. if you set the bit to 1, there are two clock cycles. if you clear the bit to 0, there is one clock cycle. the relationship between latency and frequency varies, depending on the dram speci?cation. ta b l e 5 shows an example of the timing param- eters for three nec dramsupd4516821, upd4516421, and upd4516161 drams. for the fastest access time, you should use a bit 6 bit 5 bit 4 active dal cycles 01 1 3 10 0 4 10 1 5
66 minirisc MR4010 superscalar microprocessor dram with a maximum clock frequency of 10 ns. refer to the nec users manual for further information.
minirisc MR4010 superscalar microprocessor 67 9.5 dram refresh the dram controller needs to refresh the 2048 rows in the synchronous dram every 32 milliseconds. the controller also needs to set up a 15,625 ns (15.625 m s) refresh interval. for example, if the maximum clock frequency is 66 mhz, the controller must issue a dram refresh command every 1,041 clock cycles. the dram controller has an 11-bit refresh interval timer that generates the refresh command. the refresh interval timer, shown in figure 18 , consists of one 11-bit register, referred to as the refresh register, which stores the refresh interval time; and one 11 bit-binary count down regis- ter, referred to as the refresh counter, which stores the refresh counter value, and is decremented by each system clock input. the refresh reg- ister address is shown below: when the system is initialized, the dram controller writes the refresh interval time data into the refresh register . the same data is stored in the refresh counter as the refresh counter value. the dram controller reads the contents of both registers only during testing. ta b l e 5 relationship between frequency and latency clock frequencies settings (-10) 1 (-12) 2 (-13) 3 cl rcd rc ras dal rp dpl 66mhz 55mhz 50mhz 2275321 33mhz 27mhz 25mhz 1143 2(3) 4 1(2) 5 1 1. maximum clock frequency for the 10 ns version of the dram. 2. maximum clock frequency for the 12 ns version of the dram. 3. maximum clock frequency for the 13 ns version of the dram. 4. nec recommends 2 clock cycles for dal when cl is set to 1. however, the MR4010 dram controller requires 3 clock cycles for dal. 5. nec recommends 1 clock cycle for rp when cl is set to 1. however, the MR4010 dram controller requires 2 clock cycles for rp. virtual address physical address 0x b000 0004 0x 1000 0004
68 minirisc MR4010 superscalar microprocessor figure 18 dram refresh interval timer after a cold reset, the counter stops counting. once the dram controller has written the value for the refresh interval time into the refresh register, the counter loads the same initial value and start counting by decrementing the initial value by 1 at each clock input. when the counter has counted down to 1, the dram controller sets the ref bit in the MR4010 con?guration register requesting a refresh command. the initial value is then reloaded and the process starts again. note that the counter never counts down to 0. if a dram transaction is proceeding when the dram controller issues the refresh command, the status of the refresh command is pending, and a refresh command cycle is gen- erated when the preceeding transaction has been completed. only a cold reset can stop the refresh counter. the setting of the refresh register is derived from the dram clock cycle value, the required refresh interval (15,625), and the cas latency setting (cl), which determines the number of clock cycles required before data is available. ta b l e 6 lists refresh register programming values for two microprocessors (66 mhz, and 50 mhz). you can calculate value a by dividing the refresh interval by the microprocessors clock cycle time. you can calculate the value programmed into the refresh register by subtracting the number of clock cycles required (a function of the cl refresh register (write) 31 11 10 0 reserved (0) refresh interval time refresh counter (read) 31 11 10 0 reserved (0) refresh counter value md96.275
minirisc MR4010 superscalar microprocessor 69 setting) from value a. in the ?rst example shown, the refresh register should be set to 1031 (0x407). register setting for the 80 mhz, 12.5 ns dram. 9.6 dram commands this section describes the dram commands used by MR4010 dram controller. they are the chip select commands (mcsn[1:0]), row and column addresses strobes (rasn and casn), and the write enable command (mwen). the dram controller does not use the drams self- refresh entry command and burst stop command. in addition, for a no operation (nop), the dram controller deasserts the chip select outputs mcsn[1:0] and the other control signals. ta b l e 6 refresh register programming values clock frequency clock cycle time value (a) 1 number of clock cycles required (b) 2 refresh register programmed value 3 decimal (hex) cl setting 66 mhz 15 ns 1041 10 1031 (0x407) 2 50 mhz 20 ns 781 8 773 (0x305) 1 1. value a is derived from the required refresh interval time (15,625 ns) divided by the clock cycle time (12.5 ns, and so forth). 2. number of clock cycles required is a function of the cl setting. 3. the refresh register programmed value is derived from value a minus value b (the required number of clock cycles). register bits 31 30 29 28 27-11 10 9 8 76543210 binary setting 0 0 0 0 x 1 0 0 11010110 hex value 0 x 4 d 6 decimal value not used 1 2 3 8
70 minirisc MR4010 superscalar microprocessor ta b l e 7 summarizes the settings of the mbus control signals and the dram commands they generate. the term state applies to the dram controllers internal state machine; scan indicates the scbus address bit n associated with the memory bus address bit, mapn; ~ indicates an inverted signal; ( ) indicates a dont care condition, but one in which the signals are output. ta b l e 7 summary of dram commands and mbus control signals command state mcsn[1] mcsn[0] mrasn mcasn mwen map[11] map[10] map[9:0] no operation 1 idle high high high high high (sca22) (sca21) (sca20:11) mode register set mrw 2 low low low low low sca22 sca21 sca[20:11] row active ra 3 ~sca25 sca25 low high high sca22 sca21 sca[20:11] precharge 4 pc 5 low low low high low sca22 high sca[20:11] write 6 rwc(wr) 7 ~sca25 sca25 high low low sca22 low sca24,23,[10:3] read 6 rwc(rd) 8 ~sca25 sca25 high low high sca22 low sca24,23,[10:3] cas before ras refresh cbr 9 low low low low high sca22 sca21 sca[20:11] 1. mcsn[1:0] must both be kept high for no-operation conditions 2. mrw = mode register write 3. ra = row active 4. both banks are always precharged 5. pc = precharge 6. when write or read commands are sent for a burst transaction, map[1:0] are incremented by the order of wrap around, starting from the requested address, for example, 01, 10, 11, then 00 7. rwc(wr) = write 8. rwc(rd) = read 9. cbr = cas before ras
minirisc MR4010 superscalar microprocessor 71 9.7 initializing the dram and programming the mode register before the dram controller can access the dram for a normal read or write transaction, the boot program must initialize the dram through the dram controller. after power on, the dram controller goes through the following initialization process: precharges the dram programs the drams mode register refreshes the dram array twice the cpu can initiate this process by: 1. programming the dram con?guration register. 2. programming the dram mode register by entering one of the following words at the address shown: 3. programming the dram refresh register. cas latency (cl) physical address virtual address 1 0x0010 8000 0xa010 8000 2 0x0011 0000 0xa011 0000 3 0x0011 8000 0xa011 8000
72 minirisc MR4010 superscalar microprocessor figure 19 shows the timing requirements for the dram initialization sequence. ta b l e 8 lists the signals referenced in figure 19 and in subsequent timing diagrams. the signals are in alphabetical order.
minirisc MR4010 superscalar microprocessor 73 ta b l e 8 timing signals signal name description other references aoereqp (internal) address output enable request dcinvsn dcache invalidation strobe see minirisc cw4010 superscalar microprocessor core technical manual. doereqp (internal) data output enable request dramc state state of the dram controller drrdy data ready icinvsn icache invalidation strobe see minirisc cw4010 superscalar microprocessor core technical manual. ladsn lbus address strobe signals with an l pre?x are lbus signals. you will ?nd more detailed information about these signals in lbus interface on page 28 . laoen lbus address enable la(o)p lbus address (output from MR4010) lben lbus byte enable lclkp lbus clock ldp lbus data ldip lbus write data ldop lbus read data ldoen lbus data output enable lhldap lbus hold acknowledge lholdp lbus hold request lrd(o)n lbus data (output to MR4010) lrdyn lbus data ready lrdyoen lbus data ready output enable lslrdyin (internal) lbus sampled ready map memory address signals with an m pre?x are mbus (memory bus) signals. you will ?nd more detailed information about these signals in mbus interface on page 26 . mcasn memory column address strobe mcsn memory chip select mdp memory data mdqmp memory data enable/mask mrasn memory row address strobe mwen memory write enable (sheet 1 of 2)
74 minirisc MR4010 superscalar microprocessor ta b l e 9 lists abbreviations that appear in the timing diagrams ta b l e 9 timing diagram abbreviations . scap scbus address signals with an sc pre?x are cw4010 core scbus signals. you will ?nd more detailed information about these signals in the lsi logic technical manual minirisc cw4010 superscalar microprocessor core. scben (sctben) scbus enable scbrdyn scbus ready scdp scbus data scdoen scbus data output enable schgtn scbus hold grant schrqn scbus hold request sclkp system clock sctbstn scbus burst transaction sctpwn scbus next transaction is in write page sctssn scbus transaction start strobe sctsen scbus transaction start enable sldoen sclc scbus data output enable table 8 (cont.) timing signals signal name description other references (sheet 2 of 2) abbreviation description other references mrs mode register set page 62 pc precharge command page 62 ref refresh cycle page 63
minirisc MR4010 superscalar microprocessor 75 figure 19 timing requirements for the dram initialization sequence sclkp (scbus) sctssn scaoen scbrdyn mcsn[1:0] mrasn mcasn mwen map[11] map[10] (dramc state) (pc bit) (ref bit) refresh command mode register write command precharge command 3rd wr 2nd wr 1st wr idle pc pr3 idle mrw idle cbr idle cbr idle idle idle idle idle idle idle idle idle tpr 2clk trc (mrs bit) notes: 1st wr is the write to the dram con?guration register. 2nd wr is the write to the dram mode register. 3rd wr is the write to the dram refresh register. tpr = 3, trc = 10. md96.276
76 minirisc MR4010 superscalar microprocessor 9.8 dram transactions once the dram controller has initialized the dram, it can initiate various types of dram accesses. this section shows the timing require- ments for three typical dram accesses: figure 20 shows the timing for a single burst read transaction. figure 21 ( page 78 ) shows the timing for two continuous write transactions. figure 22 ( page 79 ) shows the timing for a burst write transaction. in all cases, the dram is an 80x, 10 ns device. other timing parameters for this device are as follows: cas latency (cl) = 3. (refer to page 63 for further information about cl.) active ras to read/write command period cycles (rcd) = 3. (refer to page 63 for further information about rcd.) refresh to refresh/active command period cycles (rc) = 8. (refer to page 64 for further information about rc.) active to precharge command period (ras) = 6. (refer to page 64 for further information about ras.) precharge to active command period (rp) = 3. (refer to page 65 for further information about rp.) data in to precharge command period (dpl) = 2. (refer to page 65 for further information about dpl.) data in to active/refresh command period (dal) = 5. (refer to page 65 for further information about dal.)
minirisc MR4010 superscalar microprocessor 77 figure 20 single burst read transaction sclkp scap, scben scdp drrdyn scaoen dramc state mcsn mrasn mcasn mwen map[11] map[10] map[9:0] idle ra rcd3 rcd2 rwc1 rwc2 rwc3 mdqmp mdp rwc4 pw3 tcl pw pc pr3 (ra) idle sctbstn t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 a11 a12 a13 a14 d13 d14 a11[22] a11[21] d11 d12 d13 d14 trcd tras trp a21[24,23,10:3] a11[20:11] a11 a12 a13 a14 d11 d12 md96.277
78 minirisc MR4010 superscalar microprocessor figure 21 two continuous single write transactions t18 sclkp scap, scben scdp drrdyn scaoen dramc state mcsn mrasn mcasn mwen map[11] map[10] map[9:0] idle ra rcd3 rcd2 rwc1 pw pw mdqmp mdp pc pr3 idle ra rcd3 rcd2 rwc1 pw pw pc pr3 idle sctpwn t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t19 a1 a2 a3 d1 d2 d3 a1[22] a2[22] a1[21] a2[21] a1[20:11] a2[20:11] d1 d2 tdal tdpl tras trcd trp tdal tdpl tras trcd high a1[24,23,10:3] a2[24,23,10:3] md96.278
minirisc MR4010 superscalar microprocessor 79 figure 22 burst write transaction sclkp scap, scben scdp drrdyn scaoen dramc state mcsn mrasn mcasn mwen map[11] map[10] map[9:0] idle ra rcd3 rcd2 rwc1 rwc2 rwc3 mdqmp mdp rwc4 pw pc pr3 idle (ra) sctbstn trp t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 a1 a2 a3 a4 d1 d2 d3 d4 a1[22] a1[21] a1[20:11] a1 a2 a3 a4 d1 d2 d3 d4 trcd tras tdpl tdal a1[24,23,10:3] md96.279
80 minirisc MR4010 superscalar microprocessor 10 local i/o bus and scbus/lbus converter module this section discusses the lbus, and describes how the MR4010 interacts with the lbus through the sclc module. 10.1 lbus features the lbus is a subset of vlbus or 486 bus, which has a demultiplexed 32-bit address bus and a 32-bit data bus. lbus interface on page 28 provides a list of lbus signals. there are some differences between the lbus and the vlbus. the lbus: has no i/o space has no interrupt acknowledge cycle supports only single transactions, does not support burst transactions uses the hold/hlda type of bus arbitration has a bus retry input uses the lbus clock, lclkp the lbus is synchronized by the lbus clock, lclkp, which is derived from the cw4010 system clock, sclkp. the MR4010 asserts the lchalfn signal to divide the sclkp by 2, and drives lchalfn high to divide the clock by 4. the MR4010 then outputs the lclkp to the lbus. the MR4010 can function as the lbus master or the lbus slave. if the MR4010 is master, it starts an lbus transaction while lhldap is deas- serted. if an lbus device wants to control the lbus and initiate a bus transaction, it must ?rst take ownership of the bus by issuing a bus hold request (by asserting lholdp) to the MR4010. the MR4010 returns a bus hold acknowledge signal (by asserting lhldap) to the lbus device, granting bus ownership. when this occurs, the lbus device may initiate lbus transactions. the lbus master starts a transaction on the lbus by asserting the address strobe, (ladsn). at this time, the master must also drive valid information on the address bus and the byte enable lines. the lbus
minirisc MR4010 superscalar microprocessor 81 master uses lrdn signal to control the direction of the data transfer. the master must present the appropriate level on this signal at the same time it asserts strobe signal lrdn. during a write transaction, the master must also drive valid data on the data bus at this time. when the transaction has been successfully completed, the selected slave device asserts lrdyn, indicating that the lbus is ready for another transaction. the master must continue to drive all signals until it samples lrdyn. if the transaction is a read, the slave device must place valid data on the bus before it asserts lrdyn. 10.2 MR4010 as master on the lbus the MR4010 is the master of the lbus when the cw4010 accesses an address in the lbus area located in the physical address range 0x1100 0000 through 0xffff ffff. the lbus device must assert a data ready or bus retry signal and input it to the MR4010 within 256 sclkp cycles. otherwise, the scbus watchdog timer terminates the scbus transaction by asserting a bus error signal. figure 23 shows the timing requirements for an lbus transaction generated by the cw4010. in the example shown, the cw4010 initiates a scbus transaction at t1. the sclc module, which is part of the MR4010, checks the phase lclkp clock. at t4 and t5, the sclc asserts address strobe, ladsn. during a write transaction, the sclc must output data on the lbus on the rising edge of lclkp. the lbus transaction starts at t4. at t12, the sclc samples the lrdyn signal on the rising edge of lclkp. the sclc asserts the scbus data ready signal, scbrdyn, at t13. at the same time it asserts the bus sizing request signal, scb32n. during a read transaction, the sclc samples data on the lbus when it samples lrdyn. if the transaction is a write transaction, the cw4010 places data on the scbus at t13.
82 minirisc MR4010 superscalar microprocessor figure 23 timing requirements for an scbus-to-lbus transaction sclkp scap, scben scdp (read) sldoen sctssn scdoen scbrdyn, scb32n scdp (write) read write read write sl0 sl0 sl1 sl2 sl2 sl3 sl3 sl3 sl3 sl3 sl0 sl1 sl3 sl3 sl3 sl4 sl0 sl-state sctsen lclkp adsreqp ladsn aoereqp laoen lap, lben lrdn lrdyn lslrdyin ldp (read) ldp (write) doereqp ldoen read write read write read write t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 wd rd wd rd md96.280
minirisc MR4010 superscalar microprocessor 83 10.3 MR4010 as slave on the lbus MR4010 functions as a slave on the lbus when an lbus device, such as a sonic ethernet controller, initiates a bus transaction. if, for example, the ethernet controller wishes to access the system dram, it does this through the dram controller, which is part of the MR4010. in this case, the MR4010 acts as a slave memory controller. the address being accessed must fall in the range 0x 0000 0000 through 0x 03ff ffff. the MR4010 does not assert the data ready signal, since the transaction is treated as a read/write between an lbus master and an lbus slave. figure 24 shows the timing requirements for this type of transaction. at t1, the MR4010 samples lholdp on the rising edge of lclkp. at t2, the sclc module, which is part of the MR4010, asserts scbus hold request, schrqn. the cw4010 asserts the scbus hold grant signal, schgtn, at t4. at t7, the sclc module asserts the lbus hold acknowl- edge signal, lhldap, on the rising edge of lclkp. while lhldap is asserted, the sclc module asserts lrdyoen to drive lrdyn. at t9 or later, the lbus master (in this example the sonic ethernet controller) starts an lbus transaction. the sclc samples ladsn on the rising edge of lclkp. if the signal is asserted, the sclc module knows the ethernet controller has initiated an lbus transaction. at t12, the sclc module decodes sampled address inputs and starts an scbus transaction if the address is in the dram area. the dram controller asserts the data ready signal, drrdyn, when a transaction is completed. at t17 and t18, the sclc module asserts lrdyn and the lbus transaction is completed.
84 minirisc MR4010 superscalar microprocessor figure 24 timing requirements for lbus-to-scbus transaction ls1 ls1 ls1 ls2 ls3 ls3 ls3 ls3 ls3 ls3 ls4 ls5 ls5 ls0 ls6 ls7 ls7 ls3 ls3 ls3 ls3 ls0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 schrqn schgtn dcinvsn icinvsn sclkp lclkp lholdp lhldap ladsn lrdyn lrdyoen lap, lben lrdn ldp (write) ldp (read) ldip (write) ldop (read) ldoen scap, scben scdp (read) scdp (write) sltssn drrdyn slaoen sldoen, slwrn a rd wd a wd wd rd rd write read read read write read write write md96.281
minirisc MR4010 superscalar microprocessor 85 10.4 scbus timeout watchdog timer the sclc module in the MR4010 has a watchdog timer that it uses to time out scbus transactions. the timer monitors the number of clock cycles for each scbus transaction generated by the cw4010. it does not care about scbus transactions to sclc internal registers, or scbus transactions generated by the sclc module, since these transactions will never result in a timeout. when the cw4010 initiates an scbus transaction, the transaction must be completed within 256 sclkp clock cycles, timed from the cycle in which sctssn is asserted until the cycle in which scbrdyn or scbrtyn is asserted. if the transaction takes longer than 256 clock cycles, the timer terminates the transaction by asserting scberrn, which causes a bus error exception. the MR4010 has two registers that control scbus timeout errors. as shown in figure 25 , they are the error status register and the error address register. the status register stores bus error detect enable (bede) and bus error detected (berr) bits. the scbus watchdog timer starts when the bede bit is set. if a timeout error occurs, the timer sets the berr bit. during the time that berr is set, the address register stores the scbus transactions address and further bus error detection is inhibited. the sclc can clear the bit by writing a 1 to it. a cold reset clears both bits. figure 25 scbus error address and status register bit format scbus error address register addr = 0x 1010 0000 (physical) scbus error status register addr = 0x 1010 0004 (physical) 31 31 0 0 1 berr reserved(0) error address [31:0] bede bede: bus error detect enable(1) berr: bus error was detected addr = 0x b010 0000 (virtual) addr = 0x b010 0004 (virtual) md96.282
86 minirisc MR4010 superscalar microprocessor 10.5 external vectored interrupt (evint) support the cw4010 has a special interrupt exception input feature called exter- nal vectored interrupt. the sclc module in the MR4010 provides test support for this feature with the exvi control register shown in figure 26 . figure 26 external vectored interrupt register bit format when the cw4010 reads an exception vector address from exvap[31:2], it writes the address to the program counter. the evia[31:2] bits in the exvi register are connected to the exvap[31:2] bus to provide the vector address. when the cw4010 accepts an evint exception, it clears the evia bits to zero indicating that the timing was correct when the cw4010 sampled exvap[31:2]. if software sets the sevi bit in the exvi register, the evint input of cw4010 is asserted and causes an exception. external vectored inter- rupts are enabled in the ccc register, and interrupts are enabled in the status register. the software must write the extended address to the evia bit at the same time that it sets the sevi bit. the nonmaskable interrupt input to MR4010, nmi, can be used to cause an external vectored interrupt, evint. this bit selects the function of the nmi/evint pin. if the bit is cleared to 0, the pin generates a nonmaskable interrupt (nmi). if the bit is set to 1, the pin generates an external vectored interrupt (evint). the address is still supplied by the evia bits. if hevi is cleared to 0, the falling edge of nmi causes an nmi exception. if hevi is set to 1, the falling edge of nmi causes an evint exception provided that the interrupt enable bit the status register is set. a cold reset clears all bits of the exvi register. exvi register addr = 0x 1010 0008 (physical) 31 0 1 sevi evia[31:2] hevi hevi: hardware external vectored interrupt addr = 0x b010 0008 (virtual) md96.283 sevi: software external vectored interrupt
minirisc MR4010 superscalar microprocessor 87 11 cache con?guration and maintenance this section describes the icache and dcache con?gurations, and explains how to maintain the caches after power is turned on. 11.1 cache con?guration MR4010 takes advantage of the largest icache and dcache available. you can use the ccc register in the cw4010 cp0 to program certain features of the caches. this allows you to evaluate the performance of different cache con?gurations and select the one most appropriate for your application. you can con?gure the icache and dcache indepen- dently. you can program the ccc register to implement the following features: select the cache operating size. smaller cache con?gurations need wider tag bits. the MR4010 uses the maximum number of words for the maximum con?guration and the widest tag bits for the minimum con?guration. to set the size, you program bits is[1:0] for the icache, and ds[1:0] for the dcache, as shown in ta b l e 8 . select between direct-mapped and two-way set-associative caching. to do this you program bits ie[1:0] for the icache and de[1:0] for the dcache, as shown in ta b l e 8 . ie1 and ie0 enable icache set-1 and set-0, respectively, and de1 and de0 enable dcache set-1 and set-0, respectively. in the example shown in ta b l e 8 , set-0 is enabled for both the icache and the dcache when you require direct mapping, and set-1 is disabled for both caches. when you select two-way set-associative caching, both sets are enabled for both caches. note that when you select two-way set-associative caching, total cache capacity is doubled, since you are using both cache sets. con?gure the dcache as scratchpad ram. prior to con?guring a set associativity as scratchpad ram, you must use cache isolation mode to program the corresponding tag memory to contain the desired physical addresses. when using isolate cache mode, stores to cache are not propagated to external memory. to initiate isolate cache mode, you set bit isc in the ccc register. once this process is complete, you can con?gure the dcache as scratchpad ram by programming bits de0 and sr0 to con?gure
88 minirisc MR4010 superscalar microprocessor dcache set-0, and de1 and sr1 to con?gure dcache set-1, as shown in ta b l e 9 . con?gure the icache as scratchpad ram. prior to con?guring set-1 as scratchpad ram, you must use cache isolation mode to program the tag memory to contain the desired physical addresses. in addi- tion, you must program the corresponding data ?elds to contain the instruction code which is to remain resident in the cache. once this process is complete, you can con?gure the icache as scratchpad ram by programming bits ie1 and ir1 to con?gure icache set-1, as shown in ta b l e 1 0 . ta b l e 1 1 dcache scratchpad ram con?guration ta b l e 1 0 cache size and accessing bit settings icache ie1 ie0 is[1:0] con?guration dcache de1 de0 ds[1:0] 00xx 1 no cache 0 1 0 0 1 kbyte direct mapped 0 1 0 1 2 kbyte direct mapped 0 1 1 0 4 kbyte direct mapped 0 1 1 1 8 kbyte direct mapped 1 1 0 0 2 kbyte two-way set-associative 1 1 0 1 4 kbyte two-way set-associative 1 1 1 0 8 kbyte two-way set-associative 1 1 1 1 16 kbyte two-way set-associative 1. the setting of these bits does not matter. bit settings dcache set-0 de0 sr0 con?guration dcache set-1 de1 sr1 0 x disabled 1 0 cache memory 1 1 scratchpad ram
minirisc MR4010 superscalar microprocessor 89 ta b l e 1 2 icache scratchpad ram con?guration 11.2 cache maintenance when power is turned on to the MR4010, valid bits in the ccc register have random values. after you have programmed the ccc register to select a cache con?guration, you must make sure that cache tag valid bits are cleared during the reset initialization period. cw4010 has the following instructions that you can use to ?ush the caches: flushid ?ushes the icache and the dcache flushi ?ushes the icache flushd ?ushes the dcache these instructions do not have any operand. to invalidate icache and dcache during reset initialization, use flushid. each ?ush instruction causes stall cycles for 256 clock cycles regardless of cache size. you must execute the instructions from the kseg1 uncached and unmapped area. 12 organization of speci?c internal signals this section describes the organization of the MR4010s clock circuitry that controls the MR4010s clock inputs and outputs, and MR4010s syn- chronization circuitry that handles exception inputs. 12.1 clock circuitry the pll circuit must supply the cw4010 core with the system clock, sclkp. figure 27 shows how the pll output is distributed to internal MR4010 modules, such as the dram controller and the sclc, as well as to the cw4010 core itself. the phase time of the sclkp inputs is the same for all internal modules. bit settings icache set-1 ie1 ir1 con?guration 0 x disabled 1 0 cache memory 1 1 scratchpad ram
90 minirisc MR4010 superscalar microprocessor the MR4010 buffers sclkp and outputs it as mclkp, which monitors the internal clock, de?nes relative ac speci?cations for sclkp synchro- nized inputs and outputs, and may be used as the dram clock. the MR4010 generates the clock for the lbus by dividing the sclkp either by 2 or by 4. sclkp is passed through a two-stage d-type ?ip-?op, as shown in figure 27 , and output to a 2:1 multiplexer, which is controlled by the lchalfn input. when lchalfn is asserted, on pin s of the multiplexer , the multiplexer outputs the clock signal on pin a and passes the clock signal through the second stage of the ?ip-?op for a second time. lchalfn is then deasserted, and output z from the mul- tiplexer outputs a clock signal that is 1/4 of the original sclkp. if lchalfn is deasserted when sclkp is initially input to the multiplexer, output z outputs a clock signal that is 1/2 of the original sclkp. the lbus clock, lclkp is buffered and used as an internal clock for the sclc. it is also output on the lbus to provide the clock for lbus devices. devices on the lbus sample all inputs on the rising edge of lclkp, and synchronize all outputs to the rising edge of lclkp. ta b l e 1 3 summarizes the clock generation process. figure 28 shows the timing requirements for the cw4010 and lbus clocks. figure 27 MR4010 pll clock circuitry note: lchalfn: 0 = 1/2, 1 = 1/4. rev. a : 1 = 1/2, 1 = 1/4. lcresetn dq qn cd internal lclkp internal sclkp (cw4010, dramc,sclc) (sclc) sclkp dq qn cd a b z s lchalfn sclkp -pin lclkp -pin lbus device clock input driver with pll output buffer internal clock buffer mclkp -pin sclkp monitor dram clock output buffer 2:1 multiplexer clock md96.284
minirisc MR4010 superscalar microprocessor 91 figure 28 timing requirements for the cw4010 and lbus clocks 12.2 exception inputs exception inputs to the MR4010 may be asynchronous. these inputs include: cold reset exception input, scresetn warm reset exception input, swresetn nonmaskable interrupt exception, snmin external interrupt exceptions, sextintn[5:0] the sclc module in the MR4010 has a synchronization circuit that synchronizes these inputs to the system clock, sclkp. as shown in figure 29 , the synchronization circuit consists of a series of d-type ?ip-?ops that are clocked on the rising edge of sclkp. the exception ta b l e 1 3 summary of MR4010 clocks clock name source frequency comments sclkp pin input sclkp dc to 66 mhz cw4010 clock mclkp sclkp same as sclkp frequency dram clock, sclkp monitor clock lclkp sclkp divided by 2, or sclkp divided by 4 1/2 or 1/4 of sclkp frequency lbus clock sclkp sclkp lclkp lclkp lclkp lclkp mclkp (pin input) (internal signal) (pin output) (internal signal...1/2) (pin output...1/2) (internal signal...1/4) (pin output...1/4) md96.285
92 minirisc MR4010 superscalar microprocessor inputs reset the ?rst stage, flip-flop a. on the rising edge of sclkp, the q output from a is passed to the d-input of flip-flop b. the next sclkp input clocks this stage, and the q output from b is passed to the d-input of the ?nal stage, which outputs synchronous exception signals on the rising edge of the third sclkp. figure 30 shows the timing requirements for the synchronization circuit. figure 29 exception inputs synchronization circuitry figure 30 timing requirements for synchronization circuit dq dq dq input sclkp synchronized output signals (cresetn wresetn nmin exintn[5:0]) asynchronous input signals (scresetn swresetn snmin sextintn[5:0]) flip-flop a flip-flop b flip-flop c md96.286 sclkp asynchronous input flip-flop a (q) synchronized signal flip-flop b (q) case-1input width less than sclkp case-2input width greater than sclkp cycle time cycle time md96.287
minirisc MR4010 superscalar microprocessor 93 13 electrical characteristics this section de?nes the electrical characteristics of the MR4010 reference device. ta b l e 1 4 lists the absolute maximum ratings of the MR4010. ta b l e 1 5 lists the recommended operating conditions for the MR4010. ta b l e 1 6 lists the capacitance of the MR4010s input and output signals. ta b l e 1 4 absolute maximum ratings symbol parameter limits (referenced to vss) unit vdd dc supply -0.3 to +3.9 v (volts) vin input voltage -1.0 to vdd +0.3 v (volts) vin 5 v compatible input voltage -1.0 to +6.5 v (volts) iin dc input current 10 ma (milliamperes) 1 tstg storage temperature range -65 to +150 ?c (degrees centigrade) 1. except for power pins. ta b l e 1 5 recommended operating conditions symbol parameter limits (referenced to vss) unit vdd dc supply, commercial 3.3 5% volts tc case temperature 0 to 85 ?c (degrees centigrade) ta b l e 1 6 input/output capacitance symbol parameter limits (referenced to vss) unit cin input capacitance 5 pf (picafarads) cout output capacitance 10 pf cio i/o buffer capacitance 15 pf
94 minirisc MR4010 superscalar microprocessor ta b l e 1 7 lists the MR4010s dc characteristics. ta b l e 1 8 lists the ac timing speci?cations for the MR4010. figure 31 shows timing relationships. the speci?cations are valid in the tempera- ture range 0C85 ?c case; vdd 3.3 v, 5%. setup and hold times, which are relevant only for inputs to the MR4010, are referenced to the rising edge of the system clock (sclkp) or the lbus clock (lclkp). the valid maximum times are equivalent to hold time for the MR4010s outputs. they are not relevant for the inputs. they are referenced to the rising edge of sclkp or lclkp. for 3-state signals, valid maximum times include the period from high z to valid and valid to high z. (z indicates the 3-state or off condition of the signal.) ta b l e 1 7 dc characteristics symbol parameter condition limits unit min. 1 typ. 2 max. 3 vil input voltage low -0.5 0.8 v (volts) vih input voltage high 2.0 vdd + 0.3 v vol output voltage low 0.2 0.4 v voh output voltage high 2.4 vdd - 0.3 v iil input leakage current vdd = max. vin = vdd or vss -10 1 10 a (microamperes) ioz 3-state output leakage current vdd = max. vin = vdd or vss -10 1 10 a 1. minimum 2. typical 3. maximum
minirisc MR4010 superscalar microprocessor 95 the buffer types referenced, b8rp , and so on, are lsi logic asic macro cells. output timing is calculated in all instances for a capacitance of 60 picofarads (pf). you can get detailed information about these cells from the lsi logic lcb500k preliminary design manual . ta b l e 1 8 MR4010 ac timing speci?cations signal name input timing reference clock input/output (i/o) buffer type setup hold output timing valid max. map[11:0 sclkp o b8rp 7.5 ns mdp[63:0] sclkp i/o bd2c 4.5 ns 2 ns 9.5 ns mcsn[1:0] sclkp o b6r 7.5 ns mrasn sclkp o b8rp 7.5 ns mcasn sclkp o b8rp 7.5 ns mwen sclkp o b8rp 7.5 ns mdqmp[7:0] sclkp o b2 7.5 ns lclkp sclkp o b12 13 ns lap[31:2] lclkp i/o bd4crf 5 ns 2 ns 10 ns ldp[31:0] lclkp i/o bd4crf 9 ns 2 ns 10 ns lben[3:0] lclkp i/o bd4crf 5 ns 2 ns 10 ns lrdn 1 lclkp i/o bd4crf 5 ns 2 ns 10 ns ladsn 1 lclkp i/o bd4crf 5 ns 2 ns 10 ns lrdyn 1 lclkp i/o bd4crf 5 ns 2 ns 10 ns lrtyn 1 lclkp i ibuff 5 ns 2 ns lholdp 1 lclkp i ibuff 5 ns 2 ns lhldap 1 lclkp o b2 10 ns scresetn 1, 2 sclkp i schmitcf 8 ns 2 ns swresetn 1, 2 sclkp i ibuff 8 ns 2ns snmin 1, 2 sclkp i ibuff 8 ns 2 ns sexintn[5:0] 1, 2 sclkp i ibuff 8 ns 2 ns 1. setup and hold times guaranteed by design. 2. these are asynchronous inputs that are synchronized in the MR4010, as described in external vectored interrupt (evint) support on page 86 . input setup and hold times specify the times these signals are sampled.
96 minirisc MR4010 superscalar microprocessor the following parameters are critical and you should check them carefully. 1. mbus outputs valid minimumdram requirement time is 1 ns. 2. lbus outputs valid minimumrelated data hold-time parameters for lbus devices. figure 31 ac timing for MR4010 inputs and outputs 14 package information this section provides packaging information for the MR4010 reference device. figure 32 shows the mechanical layout and dimensions, and the pin locations (a1, and so on). ta b l e 1 9 lists the pin assignments. valid delay reference clock (sclkp or lclkp) outputs reference clock (sclkp or lclkp) inputs outputs timing for ac inputs timing for ac outputs md96.288 input hold input setup valid maximum
minirisc MR4010 superscalar microprocessor 97 figure 32 mechanical drawing of the 299-pin cpga (ft) MR4010 device for board layout and manufacturing, obtain engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code ft. md96.fta
98 minirisc MR4010 superscalar microprocessor figure 32 (cont.) mechanical drawing of the 299-pin cpga (ft) MR4010 device
minirisc MR4010 superscalar microprocessor 99 ta b l e 1 9 MR4010 pin assignments pad # pin # signal name 1c3v dd2 2e5v dd2 3 b3 lap14 4 e6 lap13 5 c4 lap15 6 d6 lap16 7 d5 lap17 8 e7 lap18 9 b4 lap19 10 c5 lap20 11 b5 lap21 12 a5 lap22 13 c6 lap23 14 b6 lap24 15 d7 lap25 16 a6 lap26 17 c7 v dd2 18 e8 lap27 19 b7 lap28 20 d8 lap29 21 a7 lap30 22 e9 lap31 23 c8 lben0 24 d9 lben1 25 b8 lben2 26 c9 lben3 27 a8 ldp0 28 c10 ldp1 29 b9 ldp2 30 e10 ldp3 31 b10 ldp4 32 d10 v dd2 33 b11 v dd2 34 d11 ldp5 35 b12 ldp6 36 e11 ldp7 37 b13 ldp8 38 c11 ldp9 39 a14 ldp10 40 c12 ldp11 41 c13 ldp12 42 d12 v ss 43 b14 ldp13 44 e12 ldp14 45 a15 ldp15 46 d13 ldp16 47 c14 ldp17 48 e13 ldp18 49 b15 ldp19 50 a16 v dd2 51 c15 ldp20 52 b16 ldp21 53 a17 ldp22 54 c16 ldp23 55 b17 ldp24 56 d16 ldp25 57 d14 ldp26 58 c17 ldp27 59 e14 ldp28 60 b18 ldp29 61 d15 ldp30 62 b19 ldp31 63 e15 v dd2 64 d17 v dd2 65 c18 v dd2 66 e16 v dd2 67 c19 v dd2 68 f16 bendn 69 d18 frcmn 70 f17 scresetn 71 e17 swresetn 72 g16 snmin pad # pin # signal name pad # pin # signal name (sheet 1 of 3) 73 d19 sexintn0 74 e18 sexintn1 75 d20 sexintn2 76 e19 sexintn3 77 f18 sexintn4 78 e20 sexintn5 79 g17 v ss2 80 f19 v dd2 81 h16 v ss2 82 g18 brlikfn 83 h17 pcancrn 84 f20 pcanoddn 85 j16 pstalln 86 g19 scaoen 87 j17 scbrdyn 88 h18 scdoen 89 j18 sctbstn 90 g20 sctssn 91 k18 scifetn 92 h19 suspexn 93 k16 v dd2 94 j19 v ss2 95 k17 v dd2 96 k19 v dd2 97 l17 v dd2 98 l19 mclkp 99 l16 mdp0 100 m19 mdp1 101 l18 mdp2 102 n20 mdp3 103 m18 mdp4 104 n19 mdp5 105 m17 mdp6 106 p20 mdp7 107 m16 mdp8 108 n18 mdp9
100 minirisc MR4010 superscalar microprocessor table 19 (cont.) MR4010 pin assignments (sheet 2 of 3) pad # pin # signal name 109 n17 v dd2 110 p19 v dd2 111 n16 v ss 112 r20 v ss 113 p18 mdp10 114 r19 mdp11 115 t20 mdp12 116 r18 mdp13 117 t19 mdp14 118 u20 mdp15 119 t18 mdp16 120 u19 mdp17 121 p17 mdp18 122 t17 mdp19 123 p16 mdp20 124 u18 mdp21 125 r17 mdp22 126 v19 mdp23 127 r16 v dd2 128 v18 v dd2 129 u17 v dd2 130 t16 v dd2 131 w19 mdp24 132 t15 mdp25 133 w18 mdp26 134 u15 mdp27 135 v17 mdp28 136 t14 mdp29 137 u16 mdp30 138 w17 mdp31 139 v16 mdp32 140 w16 mdp33 141 x16 mdp34 142 v15 mdp35 143 w15 mdp36 144 u14 v dd2 145 t13 mdp37 146 x15 mdp38 147 u13 mdp39 148 v14 mdp40 149 t12 mdp41 150 w14 mdp42 151 u12 scanmonp 152 x14 scankzop 153 v12 scankzip 154 v13 scanenbp 155 v11 scancrop 156 w13 scancrip 157 t11 paramoutp 158 x13 zstaten 159 u11 testmp 160 w12 v ss2 161 u10 v dd2 162 w11 v dd2 163 t10 pllvss 164 w10 plllp2p 165 v10 pllagnd 166 w9 pllvdd 167 v9 pllrefp 168 w8 v ss2 169 u9 pllctrn 170 x7 pllctop 171 t9 pllenp 172 v8 plltdp 173 u8 plltstp 174 w7 plliddtp 175 t8 v ss2 176 x6 v dd2 177 v7 mdp43 178 w6 mdp44 179 x5 mdp45 180 v6 mdp46 181 w5 mdp47 182 x4 mdp48 183 v5 mdp49 184 w4 mdp50 185 u7 mdp51 186 u5 mdp52 187 t7 mdp53 188 v4 mdp54 189 u6 mdp55 190 w3 mdp56 191 t6 v dd2 192 v3 v dd2 193 u4 v dd2 194 t5 v dd2 195 w2 mdp57 196 r5 mdp58 197 v2 mdp59 198 r4 mdp60 199 u3 mdp61 200 p5 mdp62 201 t4 mdp63 202 u2 mrasn 203 t3 mcasn 204 u1 mwen 205 t2 map0 206 r3 map1 207 t1 map2 208 p4 map3 209 r2 v ss 210 n5 v ss 211 p3 v dd2 212 n4 v dd2 213 r1 map4 pad # pin # signal name pad # pin # signal name
minirisc MR4010 superscalar microprocessor 101 table 19 (cont.) MR4010 pin assignments (sheet 3 of 3) 229 j2 mdqmp3 230 k3 mdqmp4 231 h1 mdqmp5 232 j3 mdqmp6 233 h2 mdqmp7 234 j4 v ss2 235 h3 lcresetn 236 j5 lchalfn 237 g1 lrtyn 238 h4 lholdp 239 g2 lrdyn 240 h5 lrdn 241 g3 v dd2 242 f1 lhldap 243 f2 lclkp pad # pin # signal name 214 m5 map5 215 p2 map6 216 m4 map7 217 n3 map8 218 m3 map9 219 p1 map10 220 l3 map11 221 n2 mcsn0 222 l5 mcsn1 223 m2 v ss2 224 l4 v dd2 225 l2 v dd2 226 k4 mdqmp0 227 k2 mdqmp1 228 k5 mdqmp2 pad # pin # signal name 244 f3 ladsn 245 e1 lap2 246 e2 lap3 247 e3 lap4 248 1 g4 lap5 249 d2 lap6 250 g5 lap7 251 d3 lap8 252 f4 lap9 253 c2 lap10 254 e4 lap11 255 b2 lap12 256 f5 v dd2 257 d4 v dd2 286 pad # pin # signal name 1. pad 248/pin g4 is provided as an extra i/o for the user. however, it cannot be tested by lsi logic corporation, because the maximum i/o test capability is 256. notes: the following pins are used for power input vdd: a3, a9, a11, a13, a18, a20, b1, c20, d1, j20, k1, l20, m1, v20, w1, x2, x8, x10, x12, x18, x20. the following pins are used for power input vss: a2, a4, a10, a12, a19, b20, c1, h20, j1, k20, l1, m20, n1, v1, w20, x1, x3, x9, x11, x17, x19.
102 minirisc MR4010 superscalar microprocessor notes
minirisc MR4010 superscalar microprocessor 103 notes
to receive product literature, call us at 1-800-574-4286 (u.s. and canada); +32.11.300.531 (europe); 408.433.7700 (outside u.s., canada, and europe) and ask for department jds; or visit us at http://www.lsilogic.com 104 minirisc MR4010 superscalar microprocessor lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or lia- bility arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. lsi logic logo design and coreware are registered trade- marks, and minirisc is a trademark of lsi logic corpora- tion. all other brand and product names may be trademarks of their respective companies. printed in usa order no. c15017 1296.500.g doc. no. db09-000028-00 headquarters lsi logic corporation north american headquarters milpitas ca tel: 408.433.8000 fax: 408.433.8989 lsi logic europe plc european headquarters united kingdom tel: 44.1344.426544 fax: 44.1344.481039 lsi logic k.k. headquarters tokyo japan tel: 81.3.5463.7821 fax: 81.3.5463.7820 printed on recycled paper iso 9000 certified notes

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